ATXMEGA128B3-AU ATMEL [ATMEL Corporation], ATXMEGA128B3-AU Datasheet - Page 65

• Manufacturer Part Number: ATXMEGA128B3-AU
• Description: 8/16-bit Atmel XMEGA B3 Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

Notes:
8074B–AVR–02/12
Mnemonics
LAT
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
SBI
CBI
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
BREAK
NOP
SLEEP
WDR
1.
2.
Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
One extra cycle must be added when accessing Internal SRAM.
Operands
Z, Rd
Rd
Rd
Rd
Rd
Rd
Rd
s
s
A, b
A, b
Rr, b
Rd, b
Description
Load and Toggle RAM location
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Break
No Operation
Sleep
Watchdog Reset
Bit and Bit-test Instructions
MCU Control Instructions
(See specific descr. for BREAK)
(see specific descr. for Sleep)
(see specific descr. for WDR)
SREG(s)
SREG(s)
I/O(A, b)
I/O(A, b)
Rd(n+1)
Rd(n+1)
Rd(3..0)
Temp
Rd(0)
Rd(n)
Rd(7)
Rd(0)
Rd(7)
Rd(n)
Rd(n)
Rd(b)
Operation
Rd
(Z)
C
C
C
C
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
↔
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd,
(Z),
Temp ⊕ (Z)
Rd(n),
0,
Rd(7)
Rd(n+1),
0,
Rd(0)
C,
Rd(n),
Rd(7)
C,
Rd(n+1),
Rd(0)
Rd(n+1), n=0..6
Rd(7..4)
1
0
1
0
Rr(b)
T
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
XMEGA B3
Flags
None
Z,C,N,V,H
Z,C,N,V
Z,C,N,V,H
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
None
None
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
#Clocks
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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