ATxmega128D4-AU ATMEL [ATMEL Corporation], ATxmega128D4-AU Datasheet - Page 119

• Manufacturer Part Number: ATxmega128D4-AU
• Description: 8/16-bit Atmel XMEGA D4 Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

34. Errata
34.1
34.1.1
34.1.2
8135L–AVR–06/12
ATxmega16D4, ATxmega32D4
rev. E
rev. C/D
•
•
•
1.
2. CRC fails for Range CRC when end address is the last word address of a flash section
3. AWeX fault protection restore is not done correctly in Pattern Generation Mode
4. Erroneous interrupt when using Timer/Counter with QDEC
Not sampled.
ADC propagation delay is not correct when gain is used
CRC fails for Range CRC when end address is the last word address of a flash section
AWeX fault protection restore is not done correct in Pattern Generation Mode
ADC propagation delay is not correct when gain is used
The propagation delay will increase by only one ADC clock cycle for all gain setting.
Problem fix/Workaround
None.
If boot read lock is enabled, the range CRC cannot end on the last address of the application
section. If application table read lock is enabled, the range CRC cannot end on the last
address before the application table.
Problem fix/Workaround
Ensure that the end address used in Range CRC does not end at the last address before a
section with read lock enabled. Instead, use the dedicated CRC commands for complete
applications sections.
When a fault is detected the OUTOVEN register is cleared, and when fault condition is
cleared, OUTOVEN is restored according to the corresponding enabled DTI channels. For
Common Waveform Channel Mode (CWCM), this has no effect as the OUTOVEN is correct
after restoring from fault. For Pattern Generation Mode (PGM), OUTOVEN should instead
have been restored according to the DTILSBUF register.
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condi-
tion. Then, set correct OUTOVEN value and enable the DTI channels, before the direction
(DIR) register is written to enable the correct outputs again.
For PGM in cycle-by-cycle mode there is no workaround.
When the Timer/Counter is set in Dual Slope mode with QDEC enabled, an additional
underflow interrupt (and event) will be given when the counter counts from BOTTOM to one.
Problem fix/Workaround
When receiving underflow interrupt check direction and value of counter. If direction is UP
and counter value is zero, change the counter value to one. This will also remove the addi-
tional event. If the counter value is above zero, clear the interrupt flag.
XMEGA D4
119