ATxmega128D4-AU ATMEL [ATMEL Corporation], ATxmega128D4-AU Datasheet - Page 123

• Manufacturer Part Number: ATxmega128D4-AU
• Description: 8/16-bit Atmel XMEGA D4 Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

8135L–AVR–06/12
10. Configuration of PGM and CWCM not as described in XMEGA D Manual
Table 34-1.
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
12. BOD will be enabled after any reset
13. Sampled BOD in Active mode will cause noise when bandgap is used as reference
14. EEPROM page buffer always written when NVM DATA0 is written
15. Pending full asynchronous pin change interrupts will not wake the device
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),
but not Common Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode
(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.
Problem fix/Workaround
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not
return to normal operation at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
Using the BOD in sampled mode when the device is running in Active or Idle mode will add
noise on the bandgap reference for ADC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC or the Analog Comparator, the BOD
must not be set in sampled mode.
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
PGM
0
0
1
1
Configure PWM and CWCM according to this table:
CWCM
0
1
0
1
Description
PGM and CWCM disabled
PGM enabled
PGM and CWCM enabled
PGM enabled
XMEGA D4
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