ATxmega128D4-AU ATMEL [ATMEL Corporation], ATxmega128D4-AU Datasheet - Page 40

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ATxmega128D4-AU

Manufacturer Part Number
ATxmega128D4-AU
Description
8/16-bit Atmel XMEGA D4 Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

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20. TWI – Two-Wire Interface
20.1
20.2
8135L–AVR–06/12
Features
Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I
System Management Bus (SMBus) compatible. The only external hardware needed to imple-
ment the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data trans-
action by addressing a slave on the bus and telling whether it wants to transmit or receive data.
One bus can have many slaves and one or several masters that can take control of the bus. An
arbitration process handles priority if more than one master tries to transmit data at the same
time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are
separated from each other, and can be enabled and configured separately. The master module
supports multi-master bus operation and arbitration. It contains the baud rate generator. Both
100kHz and 400kHz bus frequency is supported. Quick command and smart mode can be
enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hard-
ware. 10-bit addressing is also supported. A dedicated address mask register can act as a
second address match register or as a register for address range masking. The slave continues
to operate in all sleep modes, including power-down mode. This enables the slave to wake up
the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitra-
tion lost, errors, collision, and clock hold on the bus are also detected and indicated in separate
status flags available in both master and slave modes.
Two Identical two-wire interface peripherals
Bidirectional, two-wire communication interface
Bus master and slave operation supported
Flexible slave address match functions
Slave can operate in all sleep modes, including power-down
Slave address match can wake device from all sleep modes
100kHz and 400kHz bus frequency support
Slew-rate limited output drivers
Input filter for bus noise and spike suppression
Support arbitration between start/repeated start and data bit (SMBus)
Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
– Phillips I
– System Management Bus (SMBus) compatible
– Slave operation
– Single bus master operation
– Bus master in multi-master bus environment
– Multi-master arbitration
– 7-bit and general call address recognition in hardware
– 10-bit addressing supported
– Address mask register for dual address match or address range masking
– Optional software address recognition for unlimited number of addresses
2
C compatible
XMEGA D4
2
C and
40

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