AT32UC3L064_11 ATMEL [ATMEL Corporation], AT32UC3L064_11 Datasheet - Page 85

• Manufacturer Part Number: AT32UC3L064_11
• Description: 32-bit Atmel AVR Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

10.2.4
32099HS–12/2011
SCIF
2. External reset in Shutdown mode
3. Disabling POR33 may generate spurious resets
4. Instability when exiting sleep walking
5. Clock Failure Detector (CFD) can be issued while turning off the CFD
6. Sleepwalking in idle and frozen sleep mode will mask all other PB clocks
1. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K
Before going to sleep modes where RCSYS is stopped, make sure the division factor
between CPU/HSB and PBx frequencies is less than or equal to 4.
If an external reset is asserted while the device is in Shutdown mode, the Power Manager
will register this as a Power-on reset (POR), and not as a SLEEP reset, in the Reset Cause
register (RCAUSE)
Fix/Workaround
None.
Depending on operating conditions, POR33 may generate a spurious reset in one of the fol-
lowing cases:
In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control
Interface (SCIF) to mask the POR33 reset will be ineffective
Fix/Workaround
- Do not disable POR33 using the user interface
- Do not use the SM33 supply monitor
- Do not enter Shutdown mode if a debugger is connected to the chip
If all the following operating conditions are true, exiting sleep walking might lead to
instability:
- The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and
OSCCTRL0.MODE == 0)
- A sleep mode where the OSC0 is automatically disabled is entered
- The device enters sleep walking
Fix/Workaround
Do not run OSC0 in external clock mode if sleepwalking is expected to be used.
While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will
change the main clock source to RCSYS.
Fix/Workaround
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch
back to original main clock source.
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-
ing, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.
In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K
is disabled.
Fix/Workaround
- When POR33 is disabled from the user interface
- When SM33 supply monitor is enabled
- When entering Shutdown mode while debugging the chip using JTAG or aWire interface
AT32UC3L016/32/64
85