AT32UC3L064_11 ATMEL [ATMEL Corporation], AT32UC3L064_11 Datasheet - Page 94

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AT32UC3L064_11

Manufacturer Part Number
AT32UC3L064_11
Description
32-bit Atmel AVR Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
32099HS–12/2011
3. FINE value for DFLL is not correct when dithering is disabled
4. BODVERSION register reads 0x100
5. VREGCR.DEEPMODEDISABLE bit is not readable
6. DFLL step size should be seven or lower when below 30MHz
7. Generic clock sources are kept running in sleep modes
8. DFLL clock is unstable with a fast reference clock
9. DFLLIF indicates coarse lock too early
10. DFLLIF dithering does not work
Writing to ICR masks any new SCIF interrupt received in the same clock cycle, regardless of
write value.
Fix/Workaround
For every interrupt except BODDET, SM33DET, and VREGOK the PCLKSR register can be
read to detect new interrupts. BODDET, SM33DET and VREGOK interrupts will not be gen-
erated if they occur whilst writing to the ICR register.
In open loop mode, the FINE value used by the DFLL DAC is offset by two compared to the
value written to the DFLL0CONF.FINE field. The value used by the DFLL DAC is
DFLL0CONF.FINE-0x002. If DFLL0CONF.FINE is written to 0x000, 0x001 or 0x002 the
value used by the DFLL DAC will be 0x1FE, 0x1FF, or 0x000 respectively.
Fix/Workaround
Write the desired value added by two to the DFLL0CONF.FINE field.
The BODVERSION register reads 0x100 instead of 0x101
Fix/Workaround
None.
VREGCR.DEEPMODEDISABLE bit is not readable.
Fix/Workaround
None.
If max step size is above seven, the DFLL might not lock at the correct frequency if the tar-
get frequency is below 30MHz.
Fix/Workaround
If the target frequency is below 30MHz, use a max step size (DFLL0MAXSTEP.MAXSTEP)
of seven or lower.
If a clock is used as a source for a generic clock when going to a sleep mode where clock
sources are stopped, the source of the generic clock will be kept running. Please refer to
Power Manager chapter for details about sleep modes.
Fix/Workaround
Disable generic clocks before going to sleep modes where clock sources are stopped to
save power.
The DFLL clock can be unstable when a fast clock is used as a reference clock in closed
loop mode.
Fix/Workaround
Use the 32KHz crystal oscillator clock, or a clock with a similar frequency, as DFLLIF refer-
ence clock.
The DFLLIF might indicate coarse lock too early, the DFLL will lose coarse lock and regain it
later.
Fix/Workaround
Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher.
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