AT32UC3L064_11 ATMEL [ATMEL Corporation], AT32UC3L064_11 Datasheet - Page 97

• Manufacturer Part Number: AT32UC3L064_11
• Description: 32-bit Atmel AVR Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

10.4.10
10.4.11
10.4.12
10.4.13
32099HS–12/2011
FREQM
GPIO
USART
SPI
1. Measured clock (CLK_MSR) sources 15-17 are shifted
2. GCLK5 can not be used as source for the CLK_MSR
1. GPIO interrupt can not be cleared when interrupts are disabled
2. VERSION register reads 0x210
1. The RTS output does not function correctly in hardware handshaking mode
1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
2. Disabling SPI has no effect on the SR.TDRE bit
CLKSEL = 14 selects the RC120M AW clock, CLKSEL = 15 selects the RC120M clock, and
CLKSEL = 16 selects the RC32K clock as source for the measured clock (CLK_MSR).
Fix/Workaround
None.
The frequency for GCLK5 can not be measured by the FREQM.
Fix/Workaround
None.
The GPIO interrupt can not be cleared unless the interrupt is enabled for the pin.
Fix/Workaround
Enable interrupt for the corresponding pin, then clear the interrupt.
The VERSION register reads 0x210 instead of 0x211.
Fix/Workaround
None.
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
AT32UC3L016/32/64
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