LPC2109FBD64/01 NXP [NXP Semiconductors], LPC2109FBD64/01 Datasheet

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LPC2109FBD64/01

Manufacturer Part Number
LPC2109FBD64/01
Description
Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN
Manufacturer
NXP [NXP Semiconductors]
Datasheet

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1. General description
2. Features
2.1 Key features brought by LPC2109/2119/2129/01 devices
2.2 Key features common for all devices
The LPC2109/2119/2129 are based on a 16/32-bit ARM7TDMI-S CPU with real-time
emulation and embedded trace support, together with 64/128/256 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at maximum clock rate. For critical code size
applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with
minimal performance penalty.
With their compact 64-pin package, low power consumption, various 32-bit timers,
4-channel 10-bit ADC, two advanced CAN channels, PWM channels and 46 fast GPIO
lines with up to nine external interrupt pins these microcontrollers are particularly suitable
for automotive and industrial control applications, as well as medical systems and
fault-tolerant maintenance buses. With a wide range of additional serial communications
interfaces, they are also suited for communication gateways and protocol converters as
well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2109/2119/2129 will apply to devices
with and without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to
differentiate from other devices only when necessary.
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LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP
flash with 10-bit ADC and CAN
Rev. 06 — 10 December 2007
Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.
They also allow for a port pin to be read at any time regardless of its function.
Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are
5 V tolerant when configured for digital I/O function(s).
UART0/1 include fractional baud rate generator, auto-bauding capabilities and
handshake flow-control fully implemented in hardware.
Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
SPI programmable data length and master mode enhancement.
Diversified Code Read Protection (CRP) enables different security levels to be
implemented. This feature is available in LPC2109/2119/2129/00 devices as well.
General purpose timers can operate as external event counters.
16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
8/16 kB on-chip static RAM.
Product data sheet

Related parts for LPC2109FBD64/01

LPC2109FBD64/01 Summary of contents

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LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN Rev. 06 — 10 December 2007 1. General description The LPC2109/2119/2129 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with ...

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... Individual enable/disable of peripheral functions for power optimization. I Dual power supply: N CPU operating voltage range of 1. 1. I/O power supply range of 3 3 Ordering information Table 1. Type number LPC2109FBD64/00 LPC2109FBD64/01 LPC2119FBD64 LPC2119FBD64/00 LPC2119FBD64/01 LPC2109_2119_2129_6 Product data sheet Ordering information Package Name Description LQFP64 plastic low profi ...

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... NXP Semiconductors Table 1. Type number LPC2129FBD64 LPC2129FBD64/00 LPC2129FBD64/01 3.1 Ordering options Table 2. Type number LPC2109FBD64/ LPC2109FBD64/ LPC2119FBD64 LPC2119FBD64/00 128 kB LPC2119FBD64/01 128 kB LPC2129FBD64 LPC2129FBD64/00 256 kB LPC2129FBD64/01 256 kB LPC2109_2119_2129_6 Product data sheet Ordering information …continued Package Name Description LQFP64 plastic low profile quad flat package; 64 leads; ...

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NXP Semiconductors 4. Block diagram LPC2109 LPC2119 LPC2129 P0[30:27], HIGH-SPEED P0[25:0] (4) GPI/O 46 PINS TOTAL P1[31:16] ARM7 LOCAL BUS INTERNAL SRAM CONTROLLER 8/16 kB SRAM EXTERNAL (1) EINT[3:0] INTERRUPTS (1) 4 CAP0 CAPTURE/ (1) 4 CAP1 COMPARE (1) 4 ...

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NXP Semiconductors 5. Pinning information 5.1 Pinning P0[21]/PWM5/CAP1[3] 1 P0[22]/CAP0[0]/MAT0[0] 2 (1) 3 P0[23]/RD2 P1[19]/TRACEPKT3 4 (1) P0[24]/TD2 DDA(3V3) P1[18]/TRACEPKT2 8 P0[25]/RD1 9 10 TD1 P0[27]/AIN0/CAP0[1]/MAT0[1] 11 P1[17]/TRACEPKT1 12 P0[28]/AIN1/CAP0[2]/MAT0[ P0[29]/AIN2/CAP0[3]/MAT0[3] P0[30]/AIN3/EINT3/CAP0[0] ...

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NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin P0[0] to P0[31] P0[0]/TXD0/ 19 PWM1 P0[1]/RXD0/ 21 PWM3/EINT0 P0[2]/SCL/ 22 CAP0[0] P0[3]/SDA/ 26 MAT0[0]/EINT1 P0[4]/SCK0/ 27 CAP0[1] P0[5]/MISO0/ 29 MAT0[1] P0[6]/MOSI0/ 30 CAP0[2] P0[7]/SSEL0/ 31 PWM2/EINT2 P0[8]/TXD1/ 33 ...

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NXP Semiconductors Table 3. Pin description …continued Symbol Pin P0[15]/RI1/EINT2 45 P0[16]/EINT0/ 46 MAT0[2]/CAP0[2] P0[17]/CAP1[2]/ 47 SCK1/MAT1[2] P0[18]/CAP1[3]/ 53 MISO1/MAT1[3] P0[19]/MAT1[2]/ 54 MOSI1/CAP1[2] P0[20]/MAT1[3]/ 55 SSEL1/EINT3 P0[21]/PWM5/ 1 CAP1[3] P0[22]/CAP0[0]/ 2 MAT0[0] P0[23]/RD2 3 P0[24]/TD2 5 P0[25]/RD1 9 P0[27]/AIN0/ 11 ...

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NXP Semiconductors Table 3. Pin description …continued Symbol Pin P1[16]/ 16 TRACEPKT0 P1[17]/ 12 TRACEPKT1 P1[18]/ 8 TRACEPKT2 P1[19]/ 4 TRACEPKT3 P1[20]/ 48 TRACESYNC P1[21]/ 44 PIPESTAT0 P1[22]/ 40 PIPESTAT1 P1[23]/ 36 PIPESTAT2 P1[24]/ 32 TRACECLK P1[25]/EXTIN0 28 P1[26]/RTCK 24 ...

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NXP Semiconductors Table 3. Pin description …continued Symbol Pin V 63 DDA(1V8) V 23, 43, 51 DD(3V3 DDA(3V3) [1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only. LPC2109_2119_2129_6 Product data sheet Type Description I Analog 1.8 V ...

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NXP Semiconductors 6. Functional description Details of the LPC2109/2119/2129 systems and peripheral functions are described in the following sections. 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ...

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NXP Semiconductors However, the ISP flash erase command can be executed at any time (no matter whether the CRP off). Removal of CRP is achieved by erasure of full on-chip user flash. With the CRP off, full ...

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NXP Semiconductors Fig 3. LPC2109/2119/2129 memory map 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by ...

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NXP Semiconductors Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has ...

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NXP Semiconductors Table 4. Block System Control ADC CAN [1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration ...

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NXP Semiconductors 6.8 10-bit ADC The LPC2109/2119/2129 each contain a single 10-bit successive approximation ADC with four multiplexed channels. 6.8.1 Features • Measurement range • Capable of performing more than 400000 10-bit samples per ...

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NXP Semiconductors • UART1 is equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). 6.10.2 UART features available in LPC2109/2119/2129/01 only Compared to previous LPC2000 microcontrollers, UARTs in LPC2109/2119/2129/01 introduce a fractional ...

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NXP Semiconductors 6.12 SPI serial I/O controller The LPC2109/2119/2129 each contain two SPIs. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master ...

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NXP Semiconductors to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ ...

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NXP Semiconductors • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • ...

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NXP Semiconductors Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge ...

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NXP Semiconductors 6.18.2 PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator ...

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NXP Semiconductors CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are ...

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NXP Semiconductors 6.18.8 APB The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via ...

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NXP Semiconductors pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static ...

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NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) ...

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NXP Semiconductors 8. Static characteristics Table 6. Static characteristics +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply ...

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NXP Semiconductors Table 6. Static characteristics +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter Power consumption LPC2109/01, LPC2119/01, LPC2129/01 I active mode supply DD(act) current I Idle mode supply current DD(idle) I ...

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NXP Semiconductors Table 7. ADC static characteristics 3.6 V unless otherwise specified; T DDA 4.5 MHz. Symbol Parameter V analog input voltage IA C analog input ia capacitance E differential linearity D error E integral ...

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NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity ...

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NXP Semiconductors 8.1 Power consumption measurements for LPC2109/01, LPC2119/01, LPC2129/01 devices The power consumption measurements represent typical values for the given conditions. The peripherals were enabled through the PCONP register, but for these measurements, the peripherals were not configured to ...

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NXP Semiconductors 10 I DD(idle) (mA Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. amb Fig 7. Typical LPC2109/01 I DD(idle) ...

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NXP Semiconductors 45 I DD(act) (mA Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. amb Fig 9. Typical LPC2119/01 and LPC2129/01 I ...

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NXP Semiconductors 10 I DD(idle) (mA Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. amb Fig 11. Typical LPC2119/01 and LPC2129/01 ...

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NXP Semiconductors 45 I DD(act) (mA 1.65 1.70 Test conditions: Active mode entered executing code from on-chip flash; PCLK = Temp = 25 C; core voltage 1.8 V; all peripherals disabled. Fig 13. Typical LPC2109/01, LPC2119/01, ...

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NXP Semiconductors 45 I DD(act) (mA Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. Fig 15. Typical LPC2109/01, LPC2119/01, and LPC2129/ ...

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NXP Semiconductors 200 I DD(pd 160 120 Test conditions: Power-down mode entered executing code from on-chip flash. Fig 17. Typical LPC2109/01, LPC2119/01, and LPC2129/01 core power-down current I temperatures Table 8. Core voltage ...

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NXP Semiconductors Table 9. Core voltage 1 Peripheral RTC ADC CAN1/2 LPC2109_2119_2129_6 Product data sheet Typical LPC2119/01 and LPC2129/01 peripheral power consumption in active mode …continued = 25 C; all measurements in A; PCLK = amb CCLK = ...

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NXP Semiconductors 9. Dynamic characteristics Table 10. Dynamic characteristics +85 C for industrial applications; V amb Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t ...

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NXP Semiconductors 9.1 Timing V Fig 18. External clock timing LPC2109_2119_2129_6 Product data sheet 0 0.2V 0 0. CHCL Rev. 06 — 10 December 2007 LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers t ...

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NXP Semiconductors 10. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original ...

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NXP Semiconductors 11. Abbreviations Table 11. Acronym ADC AMBA APB CAN CPU DCC FIFO GPIO I/O PLL PWM RAM SPI SRAM SSI SSP TTL UART LPC2109_2119_2129_6 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus ...

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... Revision history Document ID Release date LPC2109_2119_2129_6 20071210 • Modifications: Type number LPC2109FBD64/01 has been added. • Type number LPC2119FBD64/01 has been added. • Type number LPC2129FBD64/01 has been added. • Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP) and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) have been added. • ...

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NXP Semiconductors 13. Legal information 13.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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