LPC2420FBD208 NXP [NXP Semiconductors], LPC2420FBD208 Datasheet - Page 34

• Manufacturer Part Number: LPC2420FBD208
• Description: Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2420_60_3
Preliminary data sheet
7.15.1 Features
7.16.1 Features
7.15 SPI serial I/O controller
7.16 SSP serial I/O controller
7.17 SD/MMC card interface
The LPC2420/2460 contains one SPI controller. SPI is a full duplex serial interface
designed to handle multiple masters and slaves connected to a given bus. Only a single
master and a single slave can communicate on the interface during a given data transfer.
During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and
the slave always sends 8 bits to 16 bits of data to the master.
The LPC2420/2460 contains two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD
memory cards. The SD card interface conforms to the SD Multimedia Card Specification
Version 2.11 .
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
UART3 includes an IrDA mode to support infrared communication.
Compliant with SPI specification
Synchronous, Serial, Full Duplex Communication
Combined SPI master and slave
Maximum data bit rate of one eighth of the input clock rate
8 bits to 16 bits per transfer
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
Maximum SPI bus data bit rate of one half (Master mode) and one twelfth (Slave
mode) of the input clock rate
DMA transfers supported by GPDMA
Rev. 03 — 20 November 2008
Flashless 16-bit/32-bit microcontroller
LPC2420/2460
© NXP B.V. 2008. All rights reserved.
34 of 73