MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 105
MC908JL16CFAE
Manufacturer Part Number
MC908JL16CFAE
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC908JL16CFAE.pdf
(230 pages)
- Current page: 105 of 230
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FE — Receiver Framing Error Bit
PE — Receiver Parity Error Bit
Freescale Semiconductor
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Framing error detected
0 = No framing error detected
1 = Parity error detected
0 = No parity error detected
BYTE 1
BYTE 1
READ SCS1
READ SCDR
SCRF = 1
OR = 0
BYTE 1
Figure 7-13. Flag Clearing Sequence
MC68HC908JL16 Data Sheet, Rev. 1.1
READ SCDR
READ SCS1
BYTE 2
BYTE 2
DELAYED FLAG CLEARING SEQUENCE
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
OR = 0
READ SCDR
READ SCS1
SCRF = 1
BYTE 2
OR = 0
BYTE 3
BYTE 3
READ SCDR
READ SCDR
READ SCS1
READ SCS1
SCRF = 1
SCRF = 1
BYTE 3
BYTE 3
OR = 1
OR = 0
BYTE 4
BYTE 4
I/O Registers
105
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