MC9S08SG32 FREESCALE [Freescale Semiconductor, Inc], MC9S08SG32 Datasheet - Page 181
MC9S08SG32
Manufacturer Part Number
MC9S08SG32
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S08SG32.pdf
(336 pages)
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11.1.4.4
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
11.1.4.5
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
11.1.4.6
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
11.1.4.7
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
11.2
There are no ICS signals that connect off chip.
11.3
Figure 11-1
Freescale Semiconductor
ICSTRM
ICSSC
ICSC1
ICSC2
Name
External Signal Description
Register Definition
is a summary of ICS registers.
FLL Bypassed Interna
FLL Bypassed Externa
FLL Bypassed Externa
Stop (STOP)
W
W
W
W
R
R
R
R
0
7
CLKS
BDIV
0
6
Table 11-1. ICS Register Summary
MC9S08SG32 Data Sheet, Rev. 8
RANGE
0
5
l Low Power (FBILP)
l (FBE)
l Low Power (FBELP)
IREFST
RDIV
HGO
4
TRIM
LP
3
CLKST
Chapter 11 Internal Clock Source (S08ICSV2)
EREFS
IREFS
2
ERCLKEN
IRCLKEN
OSCINIT
1
EREFSTEN
IREFSTEN
FTRIM
0
175
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