MC9S08SG32 FREESCALE [Freescale Semiconductor, Inc], MC9S08SG32 Datasheet - Page 281
MC9S08SG32
Manufacturer Part Number
MC9S08SG32
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S08SG32.pdf
(336 pages)
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Figure 17-4
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the
target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low
for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit
level about 10 cycles after starting the bit time.
Freescale Semiconductor
SPEED-UP PULSE
PERCEIVED START
TO BKGD PIN
TARGET MCU
(TARGET MCU)
HOST DRIVE
DRIVE AND
BDC CLOCK
OF BIT TIME
BKGD PIN
shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is
Figure 17-4. BDM Target-to-Host Serial Bit Timing (Logic 0)
10 CYCLES
MC9S08SG32 Data Sheet, Rev. 8
HOST SAMPLES BKGD PIN
10 CYCLES
HIGH-IMPEDANCE
SPEEDUP
PULSE
Chapter 17 Development Support
EARLIEST START
OF NEXT BIT
275
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