LM3S1911-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S1911-IQC20-A0 Datasheet - Page 118
LM3S1911-IQC20-A0
Manufacturer Part Number
LM3S1911-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S1911-IQC20-A0.pdf
(426 pages)
- Current page: 118 of 426
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Hibernation Module
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
118
Reset
Reset
Type
Type
Bit/Field
31:0
R/W
R/W
31
15
1
1
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit match 0 register for the RTC counter.
R/W
R/W
30
14
1
1
RTCM0
Name
R/W
R/W
29
13
1
1
R/W
R/W
28
12
1
1
R/W
R/W
Type
27
11
R/W
1
1
R/W
R/W
26
10
0xFFFF.FFFF
1
1
Reset
R/W
R/W
25
1
9
1
Preliminary
Description
RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
R/W
R/W
24
1
8
1
RTCM0
RTCM0
R/W
R/W
23
1
7
1
R/W
R/W
22
1
6
1
R/W
R/W
21
1
5
1
R/W
R/W
20
1
4
1
R/W
R/W
19
1
3
1
R/W
R/W
18
1
2
1
October 09, 2007
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1
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