EP7309-IB CIRRUS [Cirrus Logic], EP7309-IB Datasheet
EP7309-IB
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EP7309-IB Summary of contents
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... MaverickKey http://www.cirrus.com Low-power, System-on-chip OVERVIEW The Maverick™ EP7309 is designed for ultra-low-power applications such as digital music players, internet appliances, smart cellular phones or any hand-held device that features the added capability of digital audio decompression. The core- logic functionality of the device is built around an ARM720T processor with four-way set-associative unified cache and a write buffer ...
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... LQFP — 256-Ball PBGA — 204-Ball TFBGA ■ The fully static EP7309 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process The EP7309 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal‚ ...
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... LQFP Package Specifications ......................................................................................................24 208-Pin LQFP Pin Diagram .......................................................................................................................25 208-Pin LQFP Numeric Pin Listing ............................................................................................................26 204-Ball TFBGA Package Characteristics ...........................................................................................................29 204-Ball TFBGA Package Specifications ..................................................................................................29 204-Ball TFBGA Pinout (Top View) ...........................................................................................................30 DS507F1 High-Performance, Low-Power System on Chip © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7309 3 ...
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... EP7309 High-Performance, Low-Power System on Chip 204-Ball TFBGA Ball Listing ...................................................................................................................... 31 256-Ball PBGA Package Characteristics ............................................................................................................ 38 256-Ball PBGA Package Specifications .................................................................................................... 38 256-Ball PBGA Pinout (Top View)) ............................................................................................................ 39 256-Ball PBGA Ball Listing ........................................................................................................................ 39 JTAG Boundary Scan Signal Ordering ............................................................................................................... 43 CONVENTIONS ................................................................................................................................. 48 Acronyms and Abbreviations .............................................................................................................................. 48 Units of Measurement ......................................................................................................................................... 48 General Conventions .......................................................................................................................................... 49 Pin Description Conventions ............................................................................................................................... 49 Ordering Information ....................................................................................................................... 50 Environmental, Manufacturing, & ...
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... List of Figures Figure 1. A Maximum EP7309 Based System ..............................................................................................................11 Figure 2. Legend for Timing Diagrams .........................................................................................................................14 Figure 3. Static Memory Single Read Cycle Timing Measurement ...............................................................................16 Figure 4. Static Memory Single Write Cycle Timing Measurement ...............................................................................17 Figure 5. Static Memory Burst Read Cycle Timing Measurement ................................................................................18 Figure 6. Static Memory Burst Write Cycle Timing Measurement ................................................................................19 Figure 7 ...
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... RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7309 Universal Asynchronous Receiver/Transmitters (UARTs) The EP7309 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data ...
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... I Photo diode input Table 3. Universal Asynchronous Receiver/Transmitters Pin Assignments Digital Audio Interface (DAI) The EP7309 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with ‚ the Crystal CS43L41/42/43 low-power audio DACs and the ‚ ...
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... EINT[3] nEXTFIQ nMEDCHG/nBROM Note: Real-Time Clock The EP7309 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt. • Driven byan external 32.768 kHz crystal oscillator © ...
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... Pin Description I JTAG clock I JTAG data input O JTAG data output I JTAG async reset input I JTAG mode select I/O Pin Description (Note) O LED flasher driver Table 16. LED Flasher Pin Assignments Pins are multiplexed. See Table 18 on page 10 more information. EP7309 for ® support for 9 ...
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... Internal Boot ROM The internal 128 byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH. Packaging The EP7309 is available in a 208-pin LQFP package, 256-ball PBGA package or a 204-ball TFBGA package. Pin Multiplexing The following table shows the pin multiplexing of the DAI, SSI2 and the CODEC ...
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... System Design As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7309 CRYSTAL CRYSTAL PC CARD PC CARD SOCKET CONTROLLER ×16 FLASH FLASH ×16 FLASH FLASH EXTERNAL MEMORY- BUFFERS MAPPED EXPANSION BUFFERS ADDITIONAL I/O AND LATCHES Note: A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or DAI ...
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... EP7309 High-Performance, Low-Power System on Chip ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings DC Core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Pad Input Current Storage Temperature, No Power Recommended Operating Conditions DC core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Input / Output Voltage ...
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... VIH = V ± 0 VIL = GND ± 0.1 V Both oscillators running, CPU static, Cache enabled, LCD - mA disabled, VIH = GND ± 0.1 V Minimum standby voltage for - V state retention, internal SRAM cache, and RTC operation only EP7309 ± 0.1 V, VIL 13 ...
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... EP7309 High-Performance, Low-Power System on Chip Timings Timing Diagram Conventions This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated ...
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... Ah t MWd t MWh t MOEd t MOEh t HWd t WDd Dnv WRd t EXs t EXh © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7309 Min Typ Max Unit ...
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... EP7309 High-Performance, Low-Power System on Chip Static Memory Single Read Cycle Figure 3. Static Memory Single Read Cycle Timing Measurement Note: 1 ...
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... Address, Data, Halfword, Word, and Write hold state until next cycle. DS507F1 EXs EXh © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip EP7309 17 ...
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... EP7309 High-Performance, Low-Power System on Chip Static Memory Burst Read Cycle Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive cycles that can be driven ...
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... EXh Figure 6. Static Memory Burst Write Cycle Timing Measurement © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip EP7309 ...
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... EP7309 High-Performance, Low-Power System on Chip SSI1 Interface Parameter ADCCLK falling edge to nADCCSS deassert delay time ADCIN data setup to ADCCLK rising edge time ADCIN data hold from ADCCLK rising edge time ADCCLK falling edge to data valid delay time ADCCLK falling edge to data invalid delay time ...
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... FRd FRa t 960 990 FR_per RXs RXh TXd t 960 990 TXv t clk_high clk_low EP7309 Unit ...
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... EP7309 High-Performance, Low-Power System on Chip LCD Interface Parameter CL[2] falling to CL[1] rising delay time CL[1] falling to CL[2] rising delay time CL[1] falling to FRM transition time CL[1] falling to M transition time CL[2] rising to DD (display data) transition time L1d ...
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... High-Performance, Low-Power System on Chip Symbol t clk_per t clk_high t clk_low t JPs t JPh t JPco t JPzx t JPxz t JPh t JPs t JPco Figure 10. JTAG Timing Measurement © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7309 Min Max Units ...
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... LQFP Pin 1 Indicator 1.35 (0.053) 0.45 (0.018) 1.45 (0.057) 0.75 (0.030) Figure 11. 208-Pin LQFP Package Outline Drawing Figure 12. For pin descriptions see the EP7309 User’s Manual. © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 27.80 (1.094) 28.20 (1.110) 1.00 (0.039) BSC 0° MIN 7° MAX ...
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... Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram Note: 1. N/C should not be grounded but left as no connects. 2. Pin differences between the EP7212 and the EP7309 are bolded. DS507F1 High-Performance, Low-Power System on Chip EP7309 208-Pin LQFP (Top View) © ...
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... EP7309 High-Performance, Low-Power System on Chip 208-Pin LQFP Numeric Pin Listing Table 19. 208-Pin LQFP Numeric Pin Listing Pin Signal Type No. 1 nCS[ VDDIO Pad Pwr 3 VSSIO Pad Gnd 4 EXPCLK I/O 5 WORD Out 6 WRITE Out 7 RUN/CLKEN O 8 EXPRDY I 9 TXD[ RXD[ ...
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... A[11 VDDIO Pad Pwr VSSIO Pad Gnd D[11] I/O 1 A[10 D[10] I D[9] I D[8] I/O 1 EP7309 Reset State Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low ...
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... EP7309 High-Performance, Low-Power System on Chip Table 19. 208-Pin LQFP Numeric Pin Listing (Continued) Pin Signal Type No. 148 A[7] O 149 VSSIO Pad Gnd 150 D[7] I/O 151 nBATCHG I 152 nEXTPWR I 153 BATOK I 154 nPOR I nMEDCHG/ 155 I nBROM 156 nURESET I 157 VDDOSC Osc Pwr 158 MOSCIN Osc ...
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... Rights Reserved) High-Performance, Low-Power System on Chip BOTTOM VIEW Ø0. CORNER 0.65 12.35 13±0.05 Substrate Thickness : Ball Pitch : 0.65 Mold Thickness Ball Diam eter : : 0.3 EP7309 ...
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... EP7309 High-Performance, Low-Power System on Chip 204-Ball TFBGA Pinout (Top View VDDR EXPCLK nCS3 nCS1 nMWE N/C B WORD VDDR nCS5 nCS2 nMOE N/C RUN/ C EXPRDY VDDR nCS4 nCS0 N/C CLKEN D PB7 RXD2 VDDR E PB4 TXD2 WRITE F PB3 PB6 TDI G PB1 PB2 PB5 ...
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... Low O LCD serial display data 1 Low O LCD AC bias drive 1 Low 0 LCD pixel clock out 1 Low I/O Data I/O 2 Low O System byte address 2 Low I/O Data I/O 1 Low O System byte address © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7309 31 ...
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... EP7309 High-Performance, Low-Power System on Chip Ball Location Name Strength B15 D[6] B16 WAKEUP B17 MOSCIN B18 VSSIO B19 VSSIO B20 nURESET C1 RUN/CLKEN C2 EXPRDY C3 VDDIO C4 nCS[4] C5 nCS[0] C6 N/C C7 N/C C8 DD[0] C9 DD[3] C10 VDDCORE C11 A[0] C12 D[2] C13 A[3] C14 D[5] C15 A[6] C16 VSSOSC C17 VDDOSC C18 VSSIO C19 ...
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... GPIO port A Input ‡ JTAG data out Input ‡ 1 I/O GPIO port B Input 1 Low O System byte address 1 Low I/O Data I/O 1 Low O System byte address ‡ 1 I/O GPIO port A Input © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7309 33 ...
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... EP7309 High-Performance, Low-Power System on Chip Ball Location Name Strength J2 PA[5] J3 PA[6] J18 A[11] J19 D[13] J20 A[13]/DRA[14] K1 PA[1] K2 PA[2] K3 VDDIO K18 D[14] K19 A[14]/DRA[13] K20 D[15] L1 TXD[1] L2 LEDDRV L3 PA[3] L18 VDDIO L19 D[16] L20 A[16]/DRA[11] M1 RXD[1] M2 CTS M3 PA[0] M18 A[15]/DRA[12] M19 A[17]/DRA[10] M20 nTRST N1 DSR N2 nTEST[1] N3 PHDIN N18 D[17] N19 D[19] N20 ...
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... SSI1 ADC serial clock 1 High O Keyboard scanner column drive 1 High O Keyboard scanner column drive I JTAG clock 1 Low O Buzzer drive output 1 Low I/O Data I/O © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description Test mode select input EP7309 35 ...
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... EP7309 High-Performance, Low-Power System on Chip Ball Location Name Strength V17 A[26]/DRA[1] V18 VDDIO V19 VDDIO V20 A[24]/DRA[3] W1 VSSIO W2 VSSIO W3 VSSIO W4 PD[6]/SDQM[0] W5 TMS W6 PD[1] W7 SSITXFR W8 SSIRXFR W9 VSSCORE W10 DRIVE[1] W11 ADCOUT W12 FB[0] W13 COL[5] W14 COL[2] W15 COL[0] W16 D[30] W17 A[27]/DRA[0] W18 ...
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... High O Keyboard scanner column drive 1 High O Keyboard scanner column drive 1 Low I/O Data I/O 1 Low I/O Data I/O 1 Low I/O Data I/O 2 Low O System byte address / SDRAM address Pad power Digital I/O power, 3.3V © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7309 37 ...
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... R 3 Places Note: 1) For pin locations see Table 2) Dimensions are in millimeters (inches), and controlling dimension is millimeter 3) Before beginning any new EP7309 design, contact Cirrus Logic for the latest package information. 38 17.00 (0.669) ±0.20 (.008) 15.00 (0.590) ±0.20 (.008) D1 Pin 1 Indicator TOP VIEW D 17 ...
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... Main oscillator out Oscillator VDDOSC Oscillator power in, 2.5V power VSSIO Pad ground I/O ground nCS[5] O Chip select out VDDIO Pad power I/O ground nCS[3] O Chip select out nMOE O ROM, expansion OP enable VDDIO Pad power Digital I/O power, 3.3V N/C O EP7309 15 16 VSSIO A VDDIO nURESET B nPOR nEXTPWR C D[7] D[8] D D[9] D[10] E D[11] VDDIO F D[12] D[13] G D[14] D[15] H ...
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... EP7309 High-Performance, Low-Power System on Chip Table 21. 256-Ball PBGA Ball Listing (Continued) Ball Location Name Type B7 DD[2] O LCD serial display data B8 CL[1] O LCD line clock B9 VDDCORE Core power Digital core power, 2.5V B10 D[1] I/O Data I/O B11 A[2] O System byte address B12 A[4] O System byte address B13 ...
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... Keyboard scanner column drive D[29] I/O Data I/O D[26] I/O Data I/O O Halfword access select output VSSIO Pad ground I/O ground D[22] I/O Data I/O D[23] I/O Data I/O RTC ground Real time clock ground O Real time clock oscillator output VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground VDDIO Pad power Digital I/O power, 3.3V EP7309 41 ...
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... EP7309 High-Performance, Low-Power System on Chip Table 21. 256-Ball PBGA Ball Listing (Continued) Ball Location Name Type P6 VSSIO Pad ground I/O ground P7 VSSIO Pad ground I/O ground P8 VDDIO Pad power Digital I/O power, 3.3V P9 VSSIO Pad ground I/O ground P10 VDDIO Pad power Digital I/O power, 3.3V P11 VSSIO Pad ground I/O ground ...
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... Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Type Position I/O 17 I/O 20 I/O 23 I/O 26 I/O 29 I/O 32 I/O 35 I/O 38 I/O 41 I/O 44 I/O 47 I/O 50 I/O 53 I/O 56 I EP7309 43 ...
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... EP7309 High-Performance, Low-Power System on Chip Table 22. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No 100 101 44 PBGA Signal Ball Ball T3 N1 nEXTFIQ ...
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... Type Position I/O 179 O 182 I/O 184 O 187 O 189 I/O 191 O 194 I/O 196 O 199 I/O 201 O 204 I/O 206 O 209 I/O 211 O 214 I/O 216 O 219 I/O 221 O 224 I/O 226 O 229 I/O 231 O 234 I/O 236 O 239 I/O 241 O 244 I/O 246 O 249 I/O 251 O 254 I/O 256 O 259 I/O 261 O 264 I/O 266 O 269 I/O 271 EP7309 45 ...
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... EP7309 High-Performance, Low-Power System on Chip Table 22. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No. 148 150 151 152 153 154 155 156 161 162 163 164 165 166 169 170 171 172 173 175 176 177 178 179 184 185 ...
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... Table 22. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No. 201 202 204 205 206 207 208 1) See EP7309 Users’ Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable. DS507F1 PBGA Signal Ball Ball A7 D6 nMWE ...
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... EP7309 High-Performance, Low-Power System on Chip CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table 23 lists abbreviations and acronyms used in this data sheet. Table 23. Acronyms and Abbreviations Acronym/ Definition Abbreviation A/D analog-to-digital ADC ...
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... Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the EP7309 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “n/c” indicates a pin that is a “ ...
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... EP7309-IR Environmental, Manufacturing, & Handling Information Model Number EP7309-CB EP7309-CBZ (Lead Free) EP7309-CV EP7309-CVZ (Lead Free) EP7309-IB EP7309-IBZ (Lead Free) EP7309-IR * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 50 Package 256-pin BGA, 17mm X 17mm 208-pin LQFP. 256-pin BGA, 17mm X 17mm 204-pin BGA, 13mm X 13mm. ...
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... SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. LINUX is a registered trademark of Linus Torvalds. Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation. DS507F1 High-Performance, Low-Power System on Chip Changes © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7309 51 ...