HT83F10 HOLTEK [Holtek Semiconductor Inc], HT83F10 Datasheet - Page 25

• Manufacturer Part Number: HT83F10
• Description: Flash Type Voice OTP MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Rev. 1.00
Z floating, H output high, L output low, I Input, O output level, I,Z input floating (no pull-high)
SPI Registers
The SIMDR register is used to store the data being
transmitted and received. There are two control regis-
ters associated with the SPI interface, SIMC0 and
SIMC2 and one data register known as SIMDR. The
SIMC1 register is not used by the SPI function. Regis-
ter SIMC0 is used to control the enable/disable func-
tion, the power down control and to set the data
transmission clock frequency. Register SIMC2 is used
for other control functions such as LSB/MSB selec-
tion, write collision flag etc.
The following gives further explanation of each bit:
SDO
SCS
SCK
SDI
SIMEN
The SIMEN bit is the overall on/off control for the
SPI interface. When the SIMENbit is cleared to zero
to disable the SPI interface, the SDI, SDO, SCK and
SCS lines will be in a floating condition and the SPI
operating current will be reduced to <0.1 A at 5V.
When the bit is high the SPI interface is enabled.
Note that when the SIMEN bit changes from low to
high the contents of the SPI control registers will be
in an unknown condition and should therefore be in-
itialised by the application program.
SIM0~SIM2
These three bits control the Master/Slave selection
and also setup the SPI interface clock speed when
in the Master Mode. The SPI clock is a function of
the system clock whether it be RC type or Crystal
type. If the Slave Mode is selected then the clock
will be supplied by the external Master device.
The following gives further explanation of each bit:
TRF
The TRF bit is the Transmit/Receive Complete flag
and is cleared by the application program and can
be used to generate an interrupt. When the bit is
high the data has been transmitted or received. If
the bit is low the data is being transmitted or has not
yet been received.
Master/Salve
(SIMEN=0)
Z
Z
Z
Z
H(CPOL=0)
L(CPOL=1)
CSEN=1
I, Z
O
L
Master (SIMEN=1)
SPI Interface Pin Status
H(CPOL=0)
L(CPOL=1)
CSEN=0
I, Z
O
Z
25
SPI Communication
After the SPI interface is enabled by setting the
SIMEN bit high, then in the Master Mode, when data is
written to the SIMDR register, transmission/reception
will begin simultaneously. When the data transfer is
complete, the TRF flag will be set automatically. In the
Slave Mode, when the clock signal from the master
has been received, any data in the SIMDR register will
be transmitted and any data on the SDI pin will be
shifted into the SIMDR register. The master should
output an SCS signal before a clock signal is provided
and slave data transfers should be enabled/disabled
before/after an SCS signal is received.
WCOL
The WCOL bit is used to detect if a data collision
has occurred. If this bit is high it means that data
has been attempted to be written to the SMDR reg-
ister during a data transfer operation. This writing
operation will be ignored if data is being transferred.
The bit can be cleared by the application program.
Note that using the CSEN bit can be disabled or en-
abled via configuration option.
CSEN
The CSEN bit is used as an on/off control for the
SCS pin. If this bit is low then the SCS pin will be dis-
abled and placed into a floating condition. If the bit is
high the SCS pin will be enabled and used as a se-
lect pin.
MLS
The MLS is used to select how the data is trans-
ferred, either MSB or LSB first. Setting the bit high
will select MSB first and low for LSB first.
Note that the SIMC2 register is the same as the
SIMAR register used by the I
CSEN=0
I, Z
I, Z
O
Z
Slave (SIMEN=1)
SCS line=0
(CSEN=1)
I, Z
I, Z
I, Z
O
2
C interface.
SCS line=1
HT83FXX
(CSEN=1)
May 12, 2009
I, Z
Z
Z
Z