X4283 INTERSIL [Intersil Corporation], X4283 Datasheet

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X4283

Manufacturer Part Number
X4283
Description
CPU Supervisor with 128K EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheets

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
X4283
Manufacturer:
XICOR
Quantity:
20 000
Part Number:
X4283S8I
Manufacturer:
Intersil
Quantity:
3 950
Company:
Part Number:
X4283V8
Quantity:
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Part Number:
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CPU Supervisor with 128K EEPROM
FEATURES
• Selectable watchdog timer
• Low V
• Low power CMOS
• 128Kbits of EEPROM
• Built-in inadvertent write protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
BLOCK DIAGRAM
—Four standard reset threshold voltages
—Adjust low V
—Reset signal valid to V
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
—8-lead SOIC
—8-lead TSSOP
SDA
SCL
V
WP
special programming sequence
bytes of EEPROM array with programmable
Block Lock
S0
S1
CC
CC
detection and reset assertion
CC
protection
reset threshold voltage using
V
CC
Reset logic
Command
®
Register
Decode &
Control
Data
Logic
Threshold
1
CC
Watchdog Transition
= 1V
Data Sheet
Detector
V
TRIP
EEPROM Array
1-888-INTERSIL or 1-888-352-6832
Protect Logic
Register
Status
+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
-
DESCRIPTION
The X4283/85 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V
user’s system from low voltage conditions, resetting
the system when V
trip point. RESET/RESET is asserted until V
to proper operating level and stabilizes. Four industry
standard Vtrip thresholds are available, however, Inter-
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
Power-on and
March 29, 2005
Timer Reset
Low Voltage
out
Watchdog
Generation
Watchdog
Timebase
All other trademarks mentioned are the property of their respective owners.
Reset &
Reset
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
interval,
Copyright Intersil Americas Inc. 2005. All Rights Reserved
CC
CC
Kb=Kilobyte
falls below the set minimum V
detection circuitry protects the
the
X4283, X4285
device
128K, 16K x 8 Bit
RESET (X4283)
RESET (X4285)
activates
FN8121.0
CC
returns
the
CC

Related parts for X4283

X4283 Summary of contents

Page 1

... Reset logic March 29, 2005 DESCRIPTION The X4283/85 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock protect serial EEPROM memory in one package. This combination lowers system cost, reduces board space require- ments, and increases reliability. ...

Page 2

... SCL X4283, X4285 PIN CONFIGURATION Device Select Input Device Select Input Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V falls below the minimum V CC tive until V rises above the minimum V CC goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period ...

Page 3

... PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4283/85 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – ...

Page 4

... A0h Figure 3. Sample V Reset Circuit TRIP 4.7K RESET V TRIP Adj. 4 X4283, X4285 Resetting the higher or This procedure is used to set the V TRIP voltage level. For example, if the current V and the new V be reset. When V thing less than 1.7V. This procedure must be used to TRIP set the voltage to a lower value ...

Page 5

... Control Register" below. The user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores WD1, WD0, BP2, BP1, and BP0. The X4283/85 will not acknowledge any data bytes written after the first byte is entered. ...

Page 6

... The state of the Control Register can be read at any time by performing a random read at address FFFFh. Only one byte is read by each register read operation. The X4283/85 resets itself after the first byte is read. The master should supply a stop condition to be con- sistent with the bus protocol, but a stop is not required to end this operation ...

Page 7

... A read operation occurring between any of the previ- ous operations will not interrupt the register write operation. Figure 5. Valid Data Changes on the SDA Bus SCL SDA 7 X4283, X4285 Memory Array Block Protect Block Protected Writes Blocked Writes Blocked Writes Blocked Writes Blocked – ...

Page 8

... Data Output from Receiver START 8 X4283, X4285 Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence ...

Page 9

... Signals from the Slave 9 X4283, X4285 eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the inter- nal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master ...

Page 10

... ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 11. 10 X4283, X4285 Address Pointer Address Ends Here 60 Addr = 8 Figure 11 ...

Page 11

... Signals from the Slave 11 X4283, X4285 Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition ...

Page 12

... When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 15. 12 X4283, X4285 indicating it requires additional data. The device con- tinues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition ...

Page 13

... Figure 15. X4283/85 Addressing Device Identifier (X1) (X0 Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – The WEL bit is set to ‘0’. In this state it is not possi- ble to write to the device. ...

Page 14

... Min. and V Max. are for reference only and are not tested X4283, X4285 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...

Page 15

... Cb Capacitive load for each bus line Notes: (5) Typical values are for T = 25°C and total capacitance of one bus line in pF. 15 X4283, X4285 = 5V) CC Parameter A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing levels For ...

Page 16

... the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 16 X4283, X4285 t t HIGH LOW ...

Page 17

... R RESET (X4285) RESET (X4283) RESET Output Timing Symbol V Reset Trip Point Voltage, X4283/85-4.5A TRIP Reset Trip Point Voltage, X4283/85 Reset Trip Point Voltage, X4283/85-2.7A Reset Trip Point Voltage, X4283/85-2.7 t Power-up Reset Time out PURST ( Detect to Reset/Output RPD CC ( Fall Time ...

Page 18

... V V Programmed Voltage Range TRAN TRIP V V Program variation after programming (0-75°C). (Programmed at 25°C.) tv TRIP V programming parameters are periodically sampled and are not 100% tested. TRIP 18 X4283, X4285 Min. 100 450 1 100 V TRIP t TSU 00h 01h or 03h Description Typ. Max. ...

Page 19

... PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 19 X4283, X4285 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.050 (1.27) X 45° 0.0075 (0.19) 0.250" 0.010 (0.25) FOOTPRINT 0 ...

Page 20

... PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 X4283, X4285 8-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .002 (.05) .006 (.15) .0118 (.30) .010 (.25) Gage Plane Seating Plane .019 (.50) .029 (.75) Detail A (20X) ...

Page 21

... X4283S8-2.7 -40°C-85°C X4283S8I-2.7 0°C-70°C X4283V8-2.7 -40°C-85°C X4283V8I-2.7 8-Lead SOIC X4283/ -4. +70° -4.5A (-40 to +85°C) Blank = No Suffix (0 to +70° Suffix (-40 to +85° -2. +70° -2.7A (-40 to +85° -2 +70° -2.7 (-40 to +85°C) ...

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