LF3321 LODEV [LOGIC Devices Incorporated], LF3321 Datasheet
LF3321
Related parts for LF3321
LF3321 Summary of contents
Page 1
... Rounding and Limiting DESCRIPTION The LF3321 is an improved version of the LF3320 Horizontal Digital Image Filter capable of operating at speeds 111MHz. This improved speed increases flexibility and performance and enables the user to utilize this device in more applications. For example, four interleaved data streams of 27MHz can now be processed within one device ...
Page 2
... PWL t PWH SCT t HCT t SCC t HCC DCC t DIS t DIS Figure 2. LF3321 Block Diagram 12 ROUT 11-0 12 DIN 11-0 8 CAA 7-0 CENA 12 CFA 11-0 PAUSEA LDA CLK LOGIC Devices Incorporated Parameter Cycle Time Clock Pulse Width Low Clock Pulse Width High Input Setup Time ...
Page 3
... DEVICES INCORPORATED DESCRIPTION Figure 3. LF3321 Functional Block Diagram DATA REVERSAL 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1- DATA 1-16 REVERSAL 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 LOGIC Devices Incorporated 11-0 OUT RSLB CENA 3 LF3321 Horizontal Digital Image Filter Improved Performance LDB PAUSEB CFB 11-0 LDA PAUSEA 11-0 CFA Video Imaging Products Feb 5, 2003 LDS.3321-A ...
Page 4
... Bit 5 in Configuration Register 1 and Configuration Register 3 configures Filters A and B respectively for an even or odd number of taps. LOGIC Devices Incorporated Odd-Tap, Even-Symmetric Coefficient Set 4 Horizontal Digital Image Filter Improved Performance Even-Tap, Odd-Symmetric Coefficient Set Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 ...
Page 5
... LOGIC Devices Incorporated ALU ALU COEF 7 COEF 6 ODD-TAP MODE 5 Horizontal Digital Image Filter Improved Performance Delay Stage N 1 Delay Stage ALU ALU ALU COEF 7 2 COEF 6 ODD-TAP INTERLEAVE MODE Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 B COEF 7 2 COEF 6 ...
Page 6
... Figure 7 .Filter A and Filter B Round/Limit/Select Circuitry LOGIC Devices Incorporated RSLB DATA IN 3 RND 32 5 SELECT 16 32 LIMIT FILTER B RSL 16 DATA OUT 6 LF3321 Horizontal Digital Image Filter Improved Performance DATA IN RSLA 3 RND 32 5 SELECT 16 32 LIMIT FILTER A RSL 16 DATA OUT Video Imaging Products Feb 5, 2003 LDS ...
Page 7
... If a LF3321 is not the last in the cascade chain, Bit 0 of Configuration Register 5 should be set to a “1”. This will cause RIN11-0 to feed data to the reverse data path. When not cascading, Bit 0 of Configuration Register 5 should be set to a “ ...
Page 8
... Each bank can hold 256 12-bit coefficients. The banks are loaded using an LF Interface is discussed in the LF Interface LOGIC Devices Incorporated section. TM section. TM section There is a separate LF Interface TM TM section Horizontal Digital Image Filter Improved Performance for the Filter A and B banks. Coefficient bank loading Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 ...
Page 9
... DEVICES INCORPORATED Functional Description Configuration The configuration registers determine how the LF3321 operates. Tables 2 through 7 show the formats of the six configuration registers. There are three types of control registers: round, select, and limit. There and Control are sixteen round registers for Filter A and sixteen for Filter B. Each register is 32 bits wide. RSLA3-0 and Registers RSLB3-0 determine which Filter A and B round registers respectively are used for rounding ...
Page 10
... Must be set to “0” FUNCTION DESCRIPTION Filter B Limit Enable 0 : Limiting Disabled 1 : Limiting Enabled Filter A Limit Enable 0 : Limiting Disabled 1 : Limiting Enabled Reserved Must be set to “0” 10 LF3321 Horizontal Digital Image Filter Improved Performance 1 Register 2 Registers 3 Registers 4 Registers 5 Registers 6 Registers 7 Registers 8 Registers 9 Registers ...
Page 11
... REGISTER ADDRESS (HEX) A00 0 600 A01 1 601 A0E 14 60E A0F 15 60F 11 LF3321 Horizontal Digital Image Filter Improved Performance TM works. The Filter A and B LF Interfaces . When LDA goes LOW, the Filter A LF Table 11 Fltr. A Limit Regs. REGISTER ADDRESS (HEX) 0 C00 1 C01 14 C0E ...
Page 12
... Horizontal Digital Image Filter Improved Performance affecting the data used for Filter TM COEFFICIENT SET COEF ADDR COEF COEF LIMIT REGISTER W3 W4 DATA ADDR DATA DATA DATA DATA Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 ...
Page 13
... LOGIC Devices Incorporated COEFFICIENT SET 1 ADDR COEF COEF CONFIGURATION REGISTER W1 ADDR DATA 1 1 ROUND REGISTER ADDR DATA DATA LF3321 Horizontal Digital Image Filter Improved Performance COEF 7 SELECT REGISTER W2 ADDR DATA DATA DATA 3 4 Video Imaging Products Feb 5, 2003 LDS.3321-A W1 ...
Page 14
... This is done by TM and the Filter B coefficient TM can load data into their TM can load the Configuration/Control TM are used to load a TM will be given priority over the TM attempts to load data into a configuration TM will not TM will continue to function TM Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 W1 ...
Page 15
... Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 ...
Page 16
... Filter B output. Figure 16. Dual Filter Mode Matrix-vector In this mode, the LF3321 can be configured to multiply a square matrix of maximum size Multiply Mode 16), multiplied by a matrix-vector of maximum size [8,1] or [16,1]. The mathematical representation for this operation is in Figure 18. When configured in the dual filter mode, the LF3321 can process two matrix- vector multipliers simultaneously (i ...
Page 17
... DEVICES INCORPORATED Operating Modes Matrix-vector To configure the LF3321 for matrix-vector multiplication, bit 4 of Configuration Register 5 must be set to 1 (Table 7). The configuration for single filter mode or dual filter mode will still apply. Writing 012H or Multiply Mode 016H to Configuration Register 5 will configure the device for dual filter mode, [8x8][8x1] matrix-vector Continued multiplication ...
Page 18
... The Matrix Multiplication Mode is valid in the Double Wide Data/Coefficient Mode. However, there are some special considerations when this mode is desired. The LF3321 must be configured for single filter mode only, for a maximum (8x8) matrix. The user must disable the cascaded filter mode, the accumulator access mode, and the data reversal (see Table 7) ...
Page 19
... A output. This mode of operation is only valid in single filter mode. Mode To configure the LF3321 for this mode, bit 3 of Configuration Register 5 must be set to 1; this will account for the scaling function (Table 7). For 24-bit data, DIN11-0 becomes the MSB (Filter A) and RIN11-0 becomes the LSB (Filter B), bit 2 of Configuration Register 5 must be set insure correct results, the coefficient sets must be aligned appropriately ...
Page 20
... To convert the complex result into a real result, as seen at the LF3321 output, two multiplies and one accumulation is required. The cosine and sine functions are realized through the coefficient sets; consequently, multiplied by the corresponding ‘I’ and ‘Q’ data streams. To satisfy the remainder of the equation, Filter A and Filter B must be accumulated ...
Page 21
... Reverse Cascade Input 11-0 In Single Filter Mode, RIN11-0 is the 12-bit reverse cascade input port. This port is connected to ROUT11-0 of another LF3321. In Dual Filter Mode, RIN11-0 can be the 12-bit input port to Filter B. Data is latched on the rising edge of CLK. CFA11-0 — Coefficient A Input CFA11-0 is used to load data into the Filter A coefficient banks (banks 0 through 7) and the configuration/ control registers ...
Page 22
... COUT11-0 — Cascade Output In Single Filter Mode, COUT11 12-bit registered cascade output port. COUT11-0 should be connected to DIN11-0 of another LF3321. In Dual Filter Mode, COUT11 12-bit registered output port for the lower twelve bits of the 16-bit Filter B output. ROUT11-0 — Reverse Cascade Output In Single Filter Mode, ROUT11 12-bit registered cascade output port ...
Page 23
... Registers important to note that in Single Filter Mode, both SHENA and SHENB should be connected together. Both must be active to enable data loading in Single Filter Mode. SHENA is latched on the rising edge of CLK. LOGIC Devices Incorporated Horizontal Digital Image Filter Improved Performance 23 LF3321 Video Imaging Products Feb 5, 2003 LDS.3321-A ...
Page 24
... LOGIC Devices Incorporated Pause TM loading sequence is halted until PAUSEA is returned to TM section for a full discussion). TM Pause TM loading sequence is halted until PAUSEB is returned to TM section for a full discussion LF3321 Horizontal Digital Image Filter Improved Performance Video Imaging Products Feb 5, 2003 LDS.3321-A ...
Page 25
... HIGH IMPEDANCE 25 Horizontal Digital Image Filter Improved Performance Supply Voltage 3.00V < VCC 3.00V < VCC Min Typ 2.4 2.0 0.0 (Note 12 PWL CYC ENA OUTPUT ENA OUTPUT Video Imaging Products LF3321 < 3.60V O < 3.60V O Max Unit V 0.4 V 5.5 V 0.8 V +10 µA +10 µA 250 ...
Page 26
... LOGIC Devices Incorporated N = total number of device outputs capacitive load per output V = supply voltage clock frequency 26 LF3321 Horizontal Digital Image Filter Improved Performance Video Imaging Products Feb 5, 2003 LDS.3321-A ...
Page 27
... V for Z-to-0 and 0-to-Z tests, and Figure B. Threshold Levels t t ENA DIS OE 1 0 Measured V with I = –10mA and I = 10mA Measured V with I = –10mA and I = 10mA Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 3.0V Vth Vth ...
Page 28
... CFA 35 1 CFA 36 0 Plastic Quad Flatpack (Q5) 0°C to 70°C--Commercial Screening Speed 9 ns LF3321QC9 LOGIC Devices Incorporated Horizontal Digital Image Filter Improved Performance Top View 144-pin 28 LF3321 108 GND 107 COUT 11 106 COUT 10 105 COUT 9 104 COUT 8 103 COUT 7 ...