AK5380VT AKM [Asahi Kasei Microsystems], AK5380VT Datasheet - Page 13

• Manufacturer Part Number: AK5380VT
• Description: 96kHz 24Bit ADC with Single - ended Input
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
n Power down
The AK5380 is placed in the power-down mode by bringing PDN “L” and the digital filter is also reset at the same time.
This reset should always be done after power-up. In the power-down mode, the VCOM are AGND level. An analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after
4129 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2’s
complement “0”. The ADC outputs settle in the data corresponding to the input signals after the end of initialization
(Settling approximately takes the group delay time).
Notes:
n System Reset
The AK5380 should be reset once by bringing PDN “L” after power-up. The internal timing starts clocking by the rising
edge (falling edge at mode1) of LRCK after exiting from reset and power down state by MCLK.
MS0100-E-01
Internal
A/D In
A/D Out
Clock In
MCLK,LRCK,SCLK
PDN
(Analog)
(Digital)
(1) Digital output corresponding to analog input has the group delay (GD).
(2) A/D output is “0” data at the power-down state.
(3) When the external clocks (MCLK,SCLK,LRCK) are stopped, the AK5380 should be in the power-down state.
State
Normal Operation
Idle Noise
GD
Figure 5. Power-down/up sequence example
(1)
(3)
Power-down
“0”data
(2)
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4129/fs(86.021ms@fs=48kHz)
Initialize
“0”data
Idle Noise
Normal Operation
GD
[AK5380]
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