AK4343EN AKM [Asahi Kasei Microsystems], AK4343EN Datasheet - Page 27
AK4343EN
Manufacturer Part Number
AK4343EN
Description
Stereo DAC with HP/RCV/SPK-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
1.AK4343EN.pdf
(98 pages)
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ASAHI KASEI
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the
MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by
PS1-0 bits (see Table 10) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or
64fs, by BCKO bit (see Table 11).
MS0478-E-01
PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”)
Mode
Table 10. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
0
1
2
3
AK4343
Table 11. BICK Output Frequency at Master Mode
BCKO bit
MCKI
MCKO
BICK
LRCK
SDTI
PS1 bit
0
1
0
0
1
1
Figure 18. PLL Master Mode
256fs/128fs/64fs/32fs
32fs, 64fs
PS0 bit
BICK Output
1fs
Frequency
- 27 -
0
1
0
1
32fs
64fs
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
MCKO pin
MCLK
BCLK
LRCK
SDTO
256fs
128fs
64fs
32fs
Default
DSP or µP
Default
[AK4343]
2006/10
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