AK4343EN AKM [Asahi Kasei Microsystems], AK4343EN Datasheet - Page 55
AK4343EN
Manufacturer Part Number
AK4343EN
Description
Stereo DAC with HP/RCV/SPK-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
1.AK4343EN.pdf
(98 pages)
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ASAHI KASEI
When RCV bit = “1”, LOUT/ROUT pins become RCP/RCN pins, respectively. Lch/Rch signal of DAC or
LIN2/RIN2/LIN3/RIN3 is output from the RCP/RCN pins which is BTL as (L+R)/2 signal. The load impedance is 32Ω
(min). When the PMLO bit = “0”, the mono receiver output enters power-down mode and the output is Hi-Z. When the
PMLO bit is “1” and LOPS bit is “1”, mono receiver output enters power-save mode. Pop noise at power-up/down can be
reduced by changing PMLO bit at LOPS bit = “0”. When PMLO bit = “1” and LOPS bit = “0”, mono receiver output
enters in normal operation. LOVL bit set the gain of mono receiver output.
MS0478-E-01
PMLO
0
1
RCN pin
RCP pin
PMLO bit
LOPS bit
Hi-Z
LOPS
LOVL
x
1
0
Figure 49. Power-up/Power-down Timing for Receiver-Amp
0
1
Table 48. Receiver-Amp Mode Setting (x: Don’t care)
Hi-Z
Table 47. Mono Receiver Output Volume Setting
VCOM
>1ms
DAC
Normal Operation
+6dB
+8dB
Gain
Figure 48. Mono Receiver Output
Power-down
Power-save
Mode
“DACL”
0.59 x AVDD @−6dBFS
0.59 x AVDD @−8dBFS
Output Voltage (typ)
- 55 -
Normal Operation
“LOVL”
RCP
Hi-Z
Hi-Z
Default
Normal Operation
RCP pin
RCN pin
VCOM/2
RCN
Hi-Z
VCOM
>0
Hi-Z
Hi-Z
Default
[AK4343]
2006/10
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