AK4396VF AKM [Asahi Kasei Microsystems], AK4396VF Datasheet - Page 24

• Manufacturer Part Number: AK4396VF
• Description: Advanced Multi-Bit 192kHz 24-Bit ?? DAC
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
The AK4396 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF pin “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF
pins of both channels go to “L” at 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both
channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect
function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the
polarity of DZF pin.
Soft mute operation is performed at digital domain. When SMUTE pin goes to “H” or SMUTE bit goes to “1”, the output
signal is attenuated by −∞ during ATT_DATA × ATT transition time (Table 13) from the current ATT level. When
SMUTE pin is returned to “L” or SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually
changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before attenuating −∞
after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is
effective for changing the signal source without stopping the signal transmission.
Notes:
The AK4396 should be reset once by bringing PDN pin = “L” upon power-up. The analog section exits power-down
mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during
4/fs.
MS0336-E-00
Zero Detection
Soft Mute operation
System Reset
(1) ATT_DATA × ATT transition time (Table 13). For example, this time is 1020LRCK cycles (1020/fs)
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes
at ATT_DATA=255 in Normal Speed Mode.
and returned to ATT level by the same cycle.
to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”.
Attenuation
AO U T
D ZF pin
SM U T E pin or
SM U T E bit
AT T _Level
-∞
Figure 8. Soft Mute and Zero Detection
(1)
8192/fs
(4)
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G D
(2)
(1)
G D
(2)
(3)
[AK4396]
2004/08