XR16C850CM EXAR [Exar Corporation], XR16C850CM Datasheet
XR16C850CM
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XR16C850CM Summary of contents
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AUGUST 2005 GENERAL DESCRIPTION 1 The XR16C850 (850 Universal Asynchronous Receiver and Transmitter (UART). This device supports Intel and PC mode data bus interface and is software compatible to industry standard 16C450, 16C550, ST16C580 and ST16C650A UARTs. ...
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... Intel Bus Mode (SEL = VCC 16-Bit Bus Mode TX 8 CS0 9 10 CS1 -CS2 11 -BAUDOUT 12 N. XR16C850CM Mode (SEL = GND 8-Bit Bus Mode Only LPT1 TQFP A PLCC P ODE ND ODE ND SEL ...
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... REV. 2.3.1 ORDERING INFORMATION P N ART UMBER XR16C850CJ 44-Lead PLCC XR16C850CM 48-Lead TQFP XR16C850IJ 44-Lead PLCC XR16C850IM 48-Lead TQFP PIN DESCRIPTIONS N : Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain. OTE 44-P 48 AME YPE PLCC TQFP SEL NTEL US ODE NTERFACE ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 44-P 48 AME YPE PLCC TQFP CS0 CS1 CS2 INT RXRDY TXRDY# 27 ...
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REV. 2.3.1 44-P 48 AME YPE PLCC TQFP BAUD OUT# DDIS OP2 ODE NTERFACE IGNALS ONNECT ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 44-P 48 AME YPE PLCC TQFP LPT2 MODEM OR SERIAL I/O INTERFACE RTS CTS# ...
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REV. 2.3.1 44-P 48 AME YPE PLCC TQFP OP1 RS485 RESET VCC 44 42 Pwr Power supply input. All inputs are 5V tolerant except for XTAL1 for devices with ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16C850 (850) provides serial asynchronous receive data synchronization, parallel-to-serial and serial- to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the ...
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REV. 2.3.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 Host Data Bus Interface The host interface is 8 data bits wide with 3 address lines and control signals to execute bus read and write transactions. The 850 supports 2 types of host ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 2.2 PC MODE The PC mode interface includes an on-chip address decoder and interrupt selection function for the standard PC COM 1-4 ports addresses. The selection is made through three input signals: ...
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REV. 2.3.1 2.3 16-Bit Bus Interface The 16-bit bus interface is only available on the 48 pin package. The 16-bit bus mode is enabled when the BUS8/16 pin is connected to GND. In this mode, the RX data errors ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 2.7 Internal Registers The 850 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard ...
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REV. 2.3.1 2.9 Interrupts The output function of interrupt outputs change according to the operating bus type. During the Intel Bus Mode, the INT output will always be active high and MCR bit-3 will have no effect on the ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 2.11 Programmable Baud Rate Generator The UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter. The prescaler is controlled by a software bit in the MCR register. ...
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REV. 2.3.1 2.12 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO F 10 IGURE RANSMITTER PERATION IN Transm it Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control 16X Clock 2.13 ...
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REV. 2.3 IGURE ECEIVER PERATION IN NON 16X Clock Receive Tags in Data Byte LSR bits and Errors F 12 IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) 128 bytes ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 2.14 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to ...
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REV. 2.3.1 2.16 Auto CTS (Hardware) Flow Control Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is monitored to suspend/restart the local transmitter. The auto CTS flow control feature ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 2.17 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 850 will ...
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REV. 2.3.1 F 14. A RS-485 H IGURE UTO 850 UART OP1#/RS485 (0 = Transmit 1= Receive) RX 2.20 Infrared Mode The 850 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO F 15. I IGURE NFRARED TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) (FCTR bit Data Receive IR Pulse (RX pin) (FCTR bit ...
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REV. 2.3.1 2.21 Sleep Mode with Auto Wake-Up The 850 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 2.22 Internal Loopback The 850 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART ...
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REV. 2.3.1 3.0 UART INTERNAL REGISTERS The 850 has a set of configuration registers selected by address lines A0, A1 and A2. The 16C550 compatible registers can be accessed when LCR[ and the baud rate generator divisor ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO . T 8: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR ...
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REV. 2.3 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DREV RD Bit DVID TRG ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16C850 in the FIFO polled mode of operation. ...
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REV. 2.3.1 IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ...
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REV. 2.3.1 FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO pointers and FIFO level counter ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO T 10: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table ...
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REV. 2.3.1 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 LCR[3]: TX and RX Parity Select Parity or no parity can be ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable. • Logic 0 = Data registers are selected (default). • Logic 1 = Divisor latch registers are selected. 4.7 Modem Control ...
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REV. 2.3.1 MCR[7]: Clock Prescaler Select This bit overrides the CLKSEL pin selection available on the 48 and 52 pin packages. See • Logic 0 = Divide by one. The input clock from the crystal or external clock is ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO LSR[7]: Receive FIFO Data Error Flag • Logic FIFO error (default). • Logic global indicator for the sum of all error bits in the RX FIFO. ...
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REV. 2.3.1 This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. 4.11 ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Register which is located in the general register set when FCTR bit-6 = ...
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REV. 2.3.1 FCTR[7]: Programmable Trigger Register Select • Logic 0 = Registers TRG and FC selected for RX. • Logic 1 = Registers TRG and FC selected for TX. 4.19 Enhanced Feature Register (EFR) Enhanced features are enabled or ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in ...
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REV. 2.3.1 REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FLVL EFR XON1 XON2 XOFF1 XOFF2 FC I/O SIGNALS TX OP1# OP2# RTS# DTR# RXRDY# TXRDY# INT 2.97V TO 5.5V UART WITH 128-BYTE ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (48-TQFP) Thermal Resistance (44-PLCC) ELECTRICAL CHARACTERISTICS DC ELECTRICAL ...
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REV. 2.3.1 AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE APPLICABLE S YMBOL CLK Clock Pulse Duration OSC Crystal Frequency (top mark date code "EC YYWW" and older) ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE APPLICABLE S YMBOL T Delay from Chip Select to IOR# RD2 T Delay ...
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REV. 2.3 IGURE LOCK IMING CLK EXTERNAL CLOCK F 18 IGURE ODEM NPUT UTPUT IOW # Active IOW RTS# Change of state DTR# CD# CTS# DSR# INT IOR# IOR RI# 2.97V TO ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO F 19 IGURE ATA US EAD IMING IN A0-A2 Valid Address T AS CS2# CS0 CS1 IOR# IOR T RDV D0-D7 Note: Only one chipselect and one read ...
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REV. 2.3 IGURE ATA US EAD IMING IN T ASW AS# T AS1 Valid Address A0-A2 T CS1 CS2# CS0 or CS1 T RD1 IOR# IOR DDIS# T D0-D7 RDV Note: Only one ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO F 23 IGURE ATA US EAD IMING IN A0-A9 Valid Address T AS3 AEN# T RD3 IOR# T RDV D0- IGURE ATA ...
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REV. 2.3 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 (Unloading) Bit ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO F 27 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading ...
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REV. 2.3 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* Data in TX FIFO TXRDY IOW# (Loading data into FIFO) ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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REV. 2.3.1 PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL 2.97V ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO REVISION HISTORY D R ATE EVISION February 2000 Rev 1.0.0 Initial datasheet. April 2002 Rev 2.0.0 Changed to standard style format. Internal Registers are described in the order they are listed in ...
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REV. 2.3.1 GENERAL DESCRIPTION................................................................................................. 1 F ..................................................................................................................................................... 1 EATURES A ............................................................................................................................................... 1 PPLICATIONS ............................................................................................................................................................. 1 IGURE LOCK IAGRAM IGURE INOUTS N NTEL US ODE PIN DESCRIPTIONS .......................................................................................................... 3 ...
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XR16C850 2.97V TO 5.5V UART WITH 128-BYTE FIFO 3.0 UART INTERNAL REGISTERS ........................................................................................................... XR16C850 UART INTERNAL REGISTERS ................................................................................................................. 25 ABLE T 8: INTERNAL REGISTERS DESCRIPTION. S ABLE 4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................27 4.1 RECEIVE HOLDING REGISTER (RHR) - ...