71M6403-IGTR TERIDIAN [Teridian Semiconductor Corporation], 71M6403-IGTR Datasheet
71M6403-IGTR
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71M6403-IGTR Summary of contents
Page 1
... The 71M6403 also includes a 5V LCD charge pump as well as 3V LCD support with up to 168 pixels display and DIO pins. Easy conversion to ROM offers unprecedented cost structure for high volume MCCB applications ...
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... Power Up Short Circuit Detection Time..........................................................................13 80515 MPU Core..........................................................................................................................14 80515 Overview .............................................................................................................14 Memory Organization .....................................................................................................14 Special Function Registers (SFRs) ................................................................................16 Special Function Registers (Generic 80515 SFRs) ........................................................17 Special Function Registers Specific to the 71M6403 .....................................................19 Instruction Set ................................................................................................................20 UART .............................................................................................................................21 Timers and Counters......................................................................................................24 WD Timer (Software Watchdog Timer) ..........................................................................27 Interrupts ........................................................................................................................29 External Interrupts..........................................................................................................32 Interrupt Priority Level Structure ...
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... I/O RAM (Configuration RAM) – Alphabetical Order.....................................................................52 CE Program and Environment......................................................................................................58 CE Program ...................................................................................................................58 Formats..........................................................................................................................58 Constants .......................................................................................................................58 Environment ...................................................................................................................58 CE Calculations..............................................................................................................59 CE RAM Locations .......................................................................................................................59 CE Front End Data (Raw Data)......................................................................................59 Input Configuration.........................................................................................................60 Accumulation Strobe Output ..........................................................................................60 Page Electronic Trip Unit © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 REV 1.0 ...
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... OPTICAL INTERFACE ..................................................................................................68 TEMPERATURE SENSOR............................................................................................68 LCD BOOST ..................................................................................................................69 LCD DRIVERS ...............................................................................................................69 RESETZ.........................................................................................................................69 COMPARATORS ...........................................................................................................69 RAM AND FLASH MEMORY .........................................................................................70 FLASH MEMORY TIMING.............................................................................................70 EEPROM INTERFACE ..................................................................................................70 Packaging Information..................................................................................................................71 Pinout (Top View)...........................................................................................................72 Pin Descriptions .............................................................................................................73 ORDERING INFORMATION ........................................................................................................75 Page Electronic Trip Unit © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 REV 1.0 ...
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... Table 16: The S1CON Bit Functions .................................................................................................................................. 23 Table 17: The TMOD Register........................................................................................................................................... 24 Table 18: TMOD Register Bit Description.......................................................................................................................... 24 Table 19: Timers/Counters Mode Description................................................................................................................... 25 Table 20: The TCON Register............................................................................................................................................ 25 Table 21: The TCON Register Bit Functions ...................................................................................................................... 25 Table 22: Timer Modes..................................................................................................................................................... 26 Page Electronic Trip Unit © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 REV 1.0 ...
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... Table 53: Selectable Controls using the DIO_DIR Bits ...................................................................................................... 36 Table 54: MPU Data Memory Map.................................................................................................................................... 36 Table 55: Liquid Crystal Display Segment Table (Typical)................................................................................................. 38 Table 56: EECTRL Status Bits ........................................................................................................................................... 41 Table 57: TMUX[3:0] Selections ....................................................................................................................................... 42 Table 58: SSI Pin Assignment .......................................................................................................................................... 43 Table 59: CHOP_EN Bits................................................................................................................................................... 48 Page Electronic Trip Unit © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 REV 1.0 ...
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... PROG FLASH 0000-FFFF (64KB) EERDSLOW EEWRSLOW EMULATOR V3P3 PORT FAULTZ RESETZ Figure 1: IC Functional Block Diagram © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 V3P3A GNDA GNDA VOLTAGE BOOST VDRV FIR LCD_IBST FILTER LCD_BSTEN GNDD GNDD VOLT ...
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... A block diagram of the chip is shown in Figure 1. A detailed description of various hardware blocks follows. The 71M6403 is optimized for fast startup. To achieve this, an external 19.6608 MHz oscillator is required to drive CK, the primary clock input. The frequency for the CK38 input is generated from the 19.6608 MHz oscillator using an inexpensive ‘ ...
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... Voltage Reference The 71M6403 includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference of the 71M6403 is trimmed in production to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient. The voltage reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register CHOP_ENA (0x2002[5:4]). The two bits in the CHOP_ENA register enable the MPU to operate the chopper circuit in regular or inverted operation “ ...
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... The Functional Description Section contains a chapter with a detailed description on controlling the CHOP_ENA register. Temperature Sensor The 71M6403 includes an on-chip temperature sensor implemented as a bandgap reference used to determine the die temperature. The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT ...
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... Page VREF VBIAS VBIAS MUX V3P3A VREF CHOP_EN VREF_DIS MUX CTRL CK32 MUX_ALT MUX_DIV Figure 3: AFE Block Diagram Computation Engine (CE) © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 ∆Σ ADC CONVERTER - FIR + FILTER FIR_LEN VREF REV 1.0 ...
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... Table 2: CE DRAM Locations for ADC Results Figure 4: Samples in Multiplexer Cycle © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Description Current input 0 Current input 1 Current input 2 Current input 3 Current input 4 Current input 5 Temperature INEUTRAL monitor 2/32768Hz = 2/32768Hz = 61.04µ ...
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... T1 could be the delay from a system wide reference clock. If the reference clock is already stable prior to application of power to the 71M6403 (using a system wide reference clock), the T1 delay is eliminated. The resultant start up delay reduces to T2 assuming a “clean” application of power to the 71M6403. ...
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... RAM). Figure 5 shows the memory map (see also Table 54). Internal and External Data Memory: Both internal and external data memory are physically located in the 71M6403 IC. Ex- ternal data memory is only meant to imply external to the 80515 MPU core. ...
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... Table 3: Stretch Memory Cycle Width © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Write signal width memrd memaddr memwr ...
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... TMOD Only a few addresses are occupied, the others are not implemented. SFRs specific to the 71M6403 are shown in bold print. Any read access to unimplemented addresses will return undefined data, while any write access will have no effect. Page Direct addressing Special Function Registers ...
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... User 2 Port, high address byte for MOVX@Ri Interrupt Request Control Register Program Status Word Baud Rate Control Register (only WDCON.7 bit used) Accumulator B Register Table 6: Special Function Registers Reset Values © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 REV 1.0 ...
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... Bank 3 Overflow flag User defined flag Parity flag, affected by hardware to indicate odd / even number of “one” bits in the Accumulator, i.e. even parity. Table 8: PSW bit functions © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 LSB - P Location (0x00 – 0x07) (0x08 – ...
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... All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P3’), an output driver, and an input buffer, therefore the MPU can output or read data through any of these ports if they are not used for alternate purposes. Special Function Registers Specific to the 71M6403 Table 10 shows the location and description of the 71M6403-specific SFRs. Register Alternative ...
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... Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1 INT6. These bits do not have any memory and are primarily intended for debug use. Refer to the External Interrupts description. Table 10: Special Function Registers © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 REV 1.0 ...
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... TX: This pin is used to output the serial data. The bytes are output LSB first. The 71M6403 has several UART-related registers, which can be read and written. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. ...
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... Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. Table 15: The S0CON Bit Functions © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 LSB TI0 RI0 LSB ...
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... Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. Table 16: The S1CON Bit Functions © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Baud Rate variable variable REV 1.0 ...
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... Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD description. Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD description. Table 18: TMOD Register Bit Description © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 LSB M1 M0 REV 1.0 ...
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... Cleared when an interrupt is processed. Interrupt 0 type control bit. Selects either the falling edge or low level on input pin to cause interrupt. Table 21: The TCON Register Bit Functions © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 LSB IE0 IT0 ...
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... Timer 1 Mode 0 YES YES Not allowed Not allowed Table 22: Timer Modes -- -- -- -- Table 23: The PCON Register Function Table 24: PCON Register Bit Description © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Mode 1 Mode 2 YES YES YES YES YES LSB -- -- REV 1.0 ...
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... Set to activate/refresh the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock cycles after it has been set. Table 28: The IEN1 Bit Functions © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 LSB ET0 EX0 ...
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... Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT. Table 32: The WDTREL Bit Functions © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 LSB IP0.1 IP0.0 ...
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... IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and IEN2. External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6403, such as the CE, DIO, EEPROM interface, comparators. ...
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... EX3=0 – disable external interrupt 3 EX2=0 – disable external interrupt 2 Table 36: The IEN1 Bit Functions - - - - Table 37: The IEN2 Register Table 38: The IEN2 Bit Functions © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 LSB EX3 EX2 LSB - - ES1 REV 1.0 ...
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... IE1 IT1 Table 39: The TCON Register Table 40: The TCON Bit Functions EX6 IEX5 IEX4 IEX3 Table 41: The IRCON Register Table 42: The IRCON Bit Functions © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 LSB IE0 IT0 LSB IEX2 REV 1.0 ...
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... Table 43: External MPU Interrupts Flag Bit IE0 IE1 IEX2 IEX3 IEX4 IEX5 IEX6 IE_ZP8 Table 44: Control Bits for External Interrupts © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Polarity Flag Reset automatic automatic falling automatic rising automatic falling automatic ...
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... IP0.x Priority Level 0 0 Level0 (lowest Level1 1 0 Level2 1 1 Level3 (highest) Table 48: Priority Levels © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 - External interrupt 2 - External interrupt 3 - External interrupt 4 - External interrupt 5 - External interrupt 6 LSB IP0.2 IP0.1 IP0.0 LSB IP1 ...
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... Timer 1 interrupt Serial channel 0 interrupt Serial channel 1 interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Table 50: Interrupt Vectors © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 0x0003 0x000B 0x0013 0x001B 0x0023 0x0083 0x004B 0x0053 0x005B ...
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... DIR1 P1 0x91[7:4] P2 DIR2 0xA1[5:0] DIO_DIR bit 0 input DIO Pin Function Table 52: DIO_DIR Control Bit © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Data Re- Data Internal resources gister Register selectable when (SFR) Name configured as DIO Location 0x80 [3:0] Yes ...
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... Static RAM Flash Memory: The 71M6403 includes 64KB of on-chip flash memory. The flash memory is intended to primarily contain MPU program code typical application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O RAM. On power-up, before enabling the CE, the MPU must copy these images to their respective memory locations. ...
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... RTC. The RTC counter chain is designed for use with a 32.768 kHz clock source. The 71M6403 requires a 19.6608 MHz master clock for proper CE filter operation. The external (low cost) ‘HC4040 counter generates an approximate clock frequency for the RTC. The ‘ ...
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... The 71M6403 contains 24 dedicated LCD segment drivers and an additional 18 multi-purpose pins which may be configured as additional LCD segment drivers (see I/O RAM register LCD_NUM). The 71M6403 is capable of driving between 96 to 168 pixels of LCD display with 25% duty cycle. At seven segments per digit, the LCD can be designed for digits for display. Since each pixel is addressed individually, the LCD display can be a combination of alphanumeric digits and enunciator symbols ...
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... In addition to the basic software watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, hardware watchdog timer (WDT) is included in the 71M6403. This timer will reset the MPU not refreshed periodically, and can be used to recover the MPU in situations where program control is lost. ...
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... Internal Voltages (VBIAS and V2P5) The 71M6403 requires two supply voltages, V3P3A, for the analog section, and V3P3D, for the digital section. Both voltages can be tied together outside the chip. The internal supply voltage V2P5 is generated by an internal regulator from the 3.3V supplies. ...
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... Issue a ‘STOP’ sequence 6 Receive the last byte from EEPROM and don’t send ACK. 9 Issue a ‘START’ sequence Others No Operation, assert ERROR bit Table 56: EECTRL Status Bits © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 -MPU_DIV Hz where REV 1.0 ...
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... V2_OK (Comparator 2 Output) digital INEUTRAL_OK (Comparator 3 Output) digital RXD (from Optical interface) digital MUX_SYNC digital CK_10M digital CK_MPU -- reserved for production test digital CK38 digital Reserved digital Reserved Table 57: TMUX[3:0] Selections © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 REV 1.0 ...
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... SCLK after MUX_SYNC (fourth SCLK if 10MHz). MUX_SYNC can be used to synchronize the fields arriving at the data logger or DSP. Page Electronic Trip Unit LCD Segment SSI Signal Output Pin SCLK SEG3 SSDATA SEG4 SFR SEG5 SRDY SEG6 Table 58: SSI Pin Assignment © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 REV 1.0 ...
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... System Timing Summary ADC, CE and SERIAL TIMING ADC MUX Frame MUX_DIV Conversions (MUX_DIV=4 is shown) 1 ADC0 ADC1 450 900 CK COUNT = CE_CYCLES + floor((CE_CYCLES + © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 2 3 ADC2 ADC3 1350 1800 MAX CK COUNT Settle S REV 1.0 ...
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... Figure 10: RTM Output Format If 16bit fields SSI_BEG Next field is delayed while SRDY is low © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 FLAG If 32bit fields If SSI_CKGATE = ...
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... CE CE MPU MPU Data Data Pre- Pre- Post- Post- Processor Processor Processor Processor I/O RAM (Configuration RAM) I/O RAM (Configuration RAM) Figure 13: MPU/CE Data Flow CE/MPU Communication © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Processed Processed Data Data REV 1.0 ...
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... Figure 15: MPU/CE Communication (Processing Sequence) Page FAULT_PULSE DIO7 Comparator STROBE DIO6 FAULT_THRESH DATA CE Figure 14: MPU/CE Communication (Functional) ACCUMULATE INTERRUPT © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 LCD SERIAL (UART0/1) MPU EEPROM (I2C) DIO CE PRAM COMPUTATION ENGINE CE DRAM REV 1.0 ...
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... Table 59: CHOP_EN Bits Accumulation Interval m+1 MUX MUX cycle n cycle 1 Re- Re- Positive Positive versed versed Figure 16: Chop Polarity w/ Automatic Chopping © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Accumulation Interval m+2 MUX MUX cycle n cycle 1 Re- Re- Positive Positive versed versed REV 1.0 ...
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... Writes to page zero, whether by MPU or ICE, are inhibited. Additionally, by setting the I/O RAM register ECK_DIS to 1, the emulator clock is disabled, inhibiting access to the program with the emulator. Page Electronic Trip Unit Program Security © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 REV 1.0 ...
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... VERSION[7:0] Digital I/O: OPT_TXDIS DIO_EEX DIO_R1[2:0] DIO_R3[2:0] DIO_R5[2:0] DIO_R7[2:0] DIO_R9[2:0] DIO_R11[2:0] LCD Display Interface: LCD_EN LCD_MODE[2:0] … © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Bit 3 Bit 2 Bit 1 TMUX[3:0] SUM_CYCLES[5:0] RTM_EN WD_OVF EX_ZP8 COMP_STAT[2:0] VREF_DIS MPU_DIV ADC_DIS MUX_ALT FLASH66Z ...
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... Bit 5 Bit 4 Digital I/O: Interrupts and WD Timer: INT6 INT5 INT4 Flash: FLSH_ERASE[7:0] SECURE FLSH_PGADR[6:0] Serial EEPROM: EEDATA[7:0] EECTRL[7:0] © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 SSI_FPOL SSI_RDYEN SSI_RDYPOL Bit 3 Bit 2 Bit 1 DIO_0[7:0] (Port 0) DIO_DIR0[7:0] (Port 1) DIO_1[7:0] DIO_DIR1[7:0] DIO_2[5:0] ...
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... Programs the direction of DIO pins 15 through 8. 1 indicates output. Ignored if the pin is not configured as I/O. R/W Programs the direction of DIO pins 21 through 16. 1 indicates output. Ignored if the pin is not configured as I/O. © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Resource Multiple NONE -- ...
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... Flash Page Erase Address FLSH_PGADR[6:0] – Flash Page Address (page 0 thru 127) that will be erased during the Page Erase cycle. (default = 0x00). Must be re-written for each new Page Erase cycle. © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 REV 1.0 ...
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... VLCD R/W The LCD bias mode. 000: 4 states, 1/3 bias 001: 3 states, 1/3 bias 010: 2 states, ½ bias 011: 3 states, ½ bias 100: static display © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 10 11 LCD ...
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... The number of states in the input multiplexer states (I0-I5 states (I0-I3 states (I0-I2 states (I0-I1) R/W MUX_SYNC enable. When high, converts SEG7 into a MUX_SYNC output. © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 DIO DIO4-21 DIO4-20 DIO4-19 DIO4-18 DIO4-17 DIO4-16 ...
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... SSI_BEG and ending with SSI_END will be sent. SSI_END must be larger than SSI_BEG. The maximum number of output words is limited by the number of SSI clocks code pass—see FIR_LEN, MUX_DIV, and SSI_10M. R/W Reserved © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 REV 1.0 ...
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... The silicon revision number. This data sheet does not apply to revisions preceding revision 000 0100. R/W Enables VREF out to the VREF pin. This feature is disabled when VREF_DIS=1. R/W Disables the internal voltage reference. © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 REV 1.0 ...
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... MUX_ALT to enable temperature measurement. The polarity of CHOP must be altered for each sample. It must also alternate for each alternate multiplexer reading. Page Electronic Trip Unit CE Program and Environment © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 REV 1.0 ...
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... Current input 1 I2 0x2A Current input 2 I3 0x2B Current input 3 I4 0x2C Current input 4 I5 0x2D Current input 5 TEMP -- Temperature INEUTRAL monitor/compara- INEUTRAL -- tor input to power fault block © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 REV 1.0 ...
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... © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 Bit CT/ROG X X CT/ROG X X CT/ROG X X CT/ROG X I4SUM CT/ROG X X CT/ROG ...
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... LSB = (IMAX/ln8) * 3.3335*10 + STR _ CNT 1 ∑ = IXSQSUM _ X IXSQ 0 CE Address Description 0x2F LSB = (IMAX/ln8) * 5.5719*10 0x31 STROBE_PULSE = (STR_CNT + 1) * 3.9673*10 © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 - peak - Peak - Peak - Peak - Peak ...
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... Thus, if the gain of a channel is 1% 16384 slow, CAL should be increased by 1%. 16384 16384 © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 14 = 16384. The gain of each channel is directly REV 1.0 ...
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... All application-specific MPU functions mentioned above under “Application Information” are available from TERIDIAN as a standard ANSI C library and as ANSI “C” source code. The code is available as part of the Demonstration Kit for the 71M6403. The Demonstration Kits come with the 71M6403 IC preprogrammed with demo firmware mounted on a functional example of a circuit breaker PCB (Demo Board) ...
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... Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. Page Electronic Trip Unit Electrical Specifications © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 −0. 0.5V -0. -0.5V to +0.5V -1mA to 1mA, -0 ...
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... Normal Operation Battery Backup CONDITION 1mA LOAD 15mA LOAD I = 1mA LOAD 15mA LOAD VIN=0V VIN=V3P3D © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 MIN TYP MAX UNIT 3.0 3.3 3 3.45 V 2.9 5.5 V -40 85 ºC MIN TYP MAX UNIT ...
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... RTM_EN = 0 ECK_DIS = 1 MPU_DIV = 3 Power save/sleep mode V3P3A=V3P3D=VLCD=3.3V ADC_DIS = 1 CE_EN = 0 MPU_DIV = 3 Normal Operation as above, except write Flash at maximum rate. CONDITION Reduce V3P3 until V2P5 drops 200mV RESETZ=1, iload=0 © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 MIN TYP MAX UNIT 8.4 9.6 mA 4.4 4.9 mA 3.7 4.2 mA 0.2 0.4 mA ...
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... VNOM(T) = VREF(22) + (T–22)TC1 + (T–22 -40ºC to +85ºC − 25º -40ºC to 85º 1mA, -1mA LOAD © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 MIN TYP MAX UNIT 1.193 1.195 1.197 2.5 kΩ ...
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... T =75º Nominal relationship: N(T − -40ºC to +85º © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 MIN TYP MAX UNIT mV -250 250 peak - kΩ 1.7 Ω/°C 355 nV/LSB ...
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... With respect to VLCD/3 -15 With respect to VLCD/2 -10 ∆I =10µA LOAD CONDITION MIN CONDITION MIN -20 -20 Vin = VBIAS - 100mV 0.8 0.8 +100mV overdrive 0.5 0.5 © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 TYP MAX UNIT CK / 1200 Hz 3.0 mA 2.6 mA 5.7 V 450 µA TYP MAX UNIT 0 V 0.2 V +10 ...
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... Electronic Trip Unit CONDITION MIN CKMPU = 4.9MHz 20,000 25°C 100 CONDITION MIN CONDITION MIN CKMPU=4.9MHz, Using interrupts CKMPU=4.9MHz, “bit-banging” DIO4/5 © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 TYP MAX UNIT 5 Cycles Cycles Years TYP MAX UNIT 42 µ 200 ...
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... LQFP PACKAGE OUTLINE (Bottom View) 14.000 +/- 0.200 0.225 +/- 0.045 Page Packaging Information 16.000 +/- 0.300 100 1 MAX. 1.600 1.50 +/- 0.10 0.50 TYP. 0.10 +/- 0.10 Side View © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 0.60 TYP> REV 1.0 ...
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... SEG37/DIO17 16 SEG38/DIO18 17 DIO_0 18 DIO_1 19 DIO_2 20 DIO_3 21 COM0 22 COM1 23 COM2 24 COM3 25 Page Electronic Trip Unit TERIDIAN 71M6403 © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 GNDD 75 RESETZ 74 V2P5 73 VBAT SEG31/DIO11 70 69 SEG30/DIO10 SEG29/DIO9 68 SEG28/DIO8 67 SEG41/DIO21 66 65 SEG40/DIO20 SEG39/DIO19 64 63 SEG27/DIO7 ...
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... Battery backup power supply pin. A battery or super-capacitor may be connected between VBAT and GNDD battery is used, connect VBAT to V3P3D. LCD power supply. The DC source for the LCD driver circuitry is connected here. No Connect © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 REV 1.0 ...
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... Emulator clock. This pin has an internal pull-up resistor. I Emulator reset. This pin has an internal pull-up resistor. For TERIDIAN internal use. This pin must be connected to GNDD via a 1kΩ I resistor. © 2006 TERIDIAN Semiconductor Corporation 71M6403 Electronic Trip Unit SEPTEMBER 2006 REV 1.0 ...
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... TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com © 2004-2006 T ERIDIAN Semiconductor Corporation Page Electronic Trip Unit ORDERING INFORMATION ORDERING NUMBER 71M6403-IGT 71M6403-IGT/F 71M6403-IGTR 71M6403-IGTR/F © 2006 TERIDIAN Semiconductor Corporation 71M6403 SEPTEMBER 2006 PACKAGE MARKING 71M6403-IGT xxxxxxxxxxxx 71M6403-IGT xxxxxxxxxxxxF ...