71M6521DE TERIDIAN [Teridian Semiconductor Corporation], 71M6521DE Datasheet
71M6521DE
Available stocks
Related parts for 71M6521DE
71M6521DE Summary of contents
Page 1
... GENERAL DESCRIPTION The TERIDIAN 71M6521DE/ highly integrated SOC with an MPU core, RTC, FLASH and LCD driver. TERIDIAN’s patented Single Converter Technology™ with a 22-bit delta-sigma ADC, four analog inputs, digital temperature compensation, precision voltage reference, battery voltage monitor, and 32-bit computation engine (CE) supports a wide range of re- sidential metering applications with very few low-cost external components ...
Page 2
... Real-Time Monitor ...........................................................................................................................14 Pulse Generator ..............................................................................................................................14 CE Functional Overview ..................................................................................................................14 80515 MPU Core ...........................................................................................................................................16 Memory Organization ......................................................................................................................16 Special Function Registers (SFRs)..................................................................................................18 Special Function Registers (Generic 80515 SFRs) .........................................................................19 Special Function Registers Specific to the 71M6521DE/FE ............................................................21 Instruction Set..................................................................................................................................22 UART...............................................................................................................................................22 Timers and Counters .......................................................................................................................25 WD Timer (Software Watchdog Timer)............................................................................................27 Interrupts .........................................................................................................................................29 On-Chip Resources .......................................................................................................................................37 Oscillator ...
Page 3
... I/O RAM MAP – In Numerical Order ..............................................................................................................70 SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order ..........................................................71 I/O RAM DESCRIPTION – Alphabetical Order ..............................................................................................72 CE Interface Description ................................................................................................................................79 CE Program.....................................................................................................................................79 Formats ...........................................................................................................................................79 Constants ........................................................................................................................................79 Environment ....................................................................................................................................79 v1.0 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 Page 101 ...
Page 4
... PINOUT (LQFP-64) .......................................................................................................................................96 PINOUT (QFN 68) .........................................................................................................................................96 Recommended PCB Land Pattern for the QFN-68 Package .........................................................................97 PIN DESCRIPTIONS .....................................................................................................................................98 Power/Ground Pins:.........................................................................................................................98 Analog Pins: ....................................................................................................................................98 Digital Pins:......................................................................................................................................99 I/O Equivalent Circuits: .................................................................................................................. 100 ORDERING INFORMATION ....................................................................................................................... 101 Page 101 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 v1.0 ...
Page 5
... Figure 39: External Components for the Emulator Interface ........................................................................................69 Figure 40: Wh Accuracy, 0.1A to 200A at 240V/50Hz and Room Temperature...........................................................93 Figure 41: Meter Accuracy over Harmonics at 240V, 30A............................................................................................93 Figure 42: Typical Meter Accuracy over Temperature Relative to 25°C.......................................................................94 v1.0 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 ...
Page 6
... Table 41: The TCON Register......................................................................................................................................31 Table 42: The TCON Bit Functions ..............................................................................................................................31 Table 43: The T2CON Bit Functions ............................................................................................................................31 Table 44: The IRCON Register ....................................................................................................................................32 Table 45: The IRCON Bit Functions.............................................................................................................................32 Table 45: External MPU Interrupts ...............................................................................................................................32 Page 101 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 v1.0 ...
Page 7
... Table 60: Available Circuit Functions (“—“ means “not active).....................................................................................50 Table 61: Frequency over Temperature .......................................................................................................................61 Table 62: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package .......................................................64 Table 63: LCD and DIO Pin Assignment by LCD_NUM for the LQFP-64 Package......................................................65 v1.0 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 ...
Page 8
... OPT_RX/ OPTICAL DIO1 OPT_TX/ MOD DIO2/ OPT_RXDIS WPULSE/ OPT_RXINV OPT_TXMOD OPT_TXE VARPULSE OPT_FDC OPT_TXINV VBIAS POWER FAULT V1 COMP_STAT Page 101 71M6521DE/71M6521FE VREF ΔΣ ADC CONVERTER VBIAS VBIAS - V3P3A + ADC_E VREF VREF FIR_LEN MCK DIV CK32 PLL ADC 32KHz CKADC 4 ...
Page 9
... AMR meters with an IR interface. A block diagram of the IC is shown in Figure 1. A detailed description of various functional blocks follows. The AFE of the 71M6521DE/FE is comprised of an input multiplexer, a delta-sigma A/D converter and a voltage reference. Input Multiplexer The input multiplexer supports up to four input signals that are applied to pins IA, VA, IB and VB of the device. Additionally, using the alternate mux selection, it has the ability to select temperature and the battery voltage ...
Page 10
... CE program. A/D Converter (ADC) A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6521DE/FE. The resolution of the ADC is programmable using the FIR_LEN register as shown in the I/O RAM section. ADC resolution can be selected bits (FIR_LEN=0 bits (FIR_LEN=1). Conversion time is two cycles of CK32 with FIR_LEN = 0 and three cycles with FIR_LEN = 1 ...
Page 11
... The internal bias voltage VBIAS (typically 1.6V) is used by the ADC when measuring the temperature and battery monitor signals. Temperature Sensor The 71M6521DE/FE includes an on-chip temperature sensor implemented as a bandgap reference used to determine the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT. ...
Page 12
... Each CE instruction word is two bytes long. Allocated flash space for the CE program cannot exceed 1024 words (2KB). The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code pass ends Page 101 71M6521DE/71M6521FE VREF VBIAS ...
Page 13
... Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE. ADDRESS (HEX) The CE of the 71M6521DE/FE is aided by support hardware that facilitates implementation of equations, pulse counters, and accumulators. This support hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and DIO_PW (pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist) ...
Page 14
... For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS = 100 and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available. Page 101 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET ...
Page 15
... It is important to note that the length of the accumulation interval, as determined by N PRE_SAMPS, is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), the resulting accumulation interval is: τ This means that accurate time measurements should be based on the RTC, not the accumulation interval. v1.0 71M6521DE/71M6521FE 13/32768Hz = 397µs ...
Page 16
... Static RAM Internal and External Data Memory: Both internal and external data memory are physically located on the 71M6521DE/FE IC. “External” data memory is only external to the 80515 MPU core. Program Memory: The 80515 can theoretically address up to 64KB of program memory space from 0x0000 to 0xFFFF. ...
Page 17
... The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal RAM. v1.0 71M6521DE/71M6521FE Stretch Value Read signals width memaddr ...
Page 18
... Only a few addresses are occupied, the others are not implemented. SFRs specific to the 652X are shown in bold print. Any read access to unimplemented addresses will return undefined data, while any write access will have no effect. The registers at 0x80, 0x88, 0x90, etc., are bit-addressable, all others are byte-addressable. Page 101 71M6521DE/71M6521FE Direct addressing Indirect addressing Byte-addressable area Bit-addressable area Register banks R0… ...
Page 19
... WDCON 0xE0 0x00 A 0xF0 0x00 B Table 8: Special Function Registers Reset Values v1.0 71M6521DE/71M6521FE Description Port 0 Stack Pointer Data Pointer Low 0 Data Pointer High 0 Data Pointer Low 1 Data Pointer High 1 Watchdog Timer Reload register UART Speed Control Timer/Counter Control Timer Mode Control ...
Page 20
... MOV DPL,#data8 generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively). Program Counter: The program counter (PC bytes wide initialized to 0x0000 after reset. This register is incremented when fetching operation code or when operating on data from program memory. Page 101 71M6521DE/71M6521FE F0 RS1 RS OV Table 9: PSW Register Flags F0 is not to be confused with the F0 flag in the CE STATUS register ...
Page 21
... MPU, for example when counting pulses issued via DIO pins that are under CE control. The technique of reading the status of or generating interrupts based on DIO pins configured as outputs, can be used to implement pulse counting. Special Function Registers Specific to the 71M6521DE/FE Table 12 shows the location and description of the 71M6521DE/FE-specific SFRs. Register Alternative SFR Name ...
Page 22
... All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the 71M6521 Software User’s Guide (SUG). UART The 71M6521DE/FE includes a UART (UART0) that can be programmed to communicate with a variety of AMR modules. A second UART (UART1) is connected to the optical port, as described in the optical port description. Page 101 ...
Page 23
... TX: This pin is used to output the serial data. The bytes are output LSB first. The 71M6521DE/FE has several UART-related registers for the control and buffering of serial data. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps ...
Page 24
... Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be S1CON.1 TI1 cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must S1CON.0 RI1 be cleared by software Page 101 71M6521DE/71M6521FE SM21 REN1 TB81 RB81 Table 16: The S1CON register Mode Description SM0 ...
Page 25
... IE0 int0 is observed. Cleared when an interrupt is processed. Interrupt 0 type control bit. Selects either the falling edge or low level on input TCON.0 IT0 pin to cause interrupt. v1.0 71M6521DE/71M6521FE TF0 TR0 IE1 IT1 Table 19: The TCON Register Table 20: The TCON Register Bit Functions © 2005-2008 TERIDIAN Semiconductor Corporation ...
Page 26
... Timer 0 acts as two independent 8-bit Timer/Counters. Note: In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow. Page 101 71M6521DE/71M6521FE M1 M0 GATE C/T ...
Page 27
... WDTREL register and the WDT is automatically reset. Since the WDT requires exact timing, firmware needs to be designed with special care in order to avoid unwanted WDT resets. TERIDIAN strongly discourages the use of the software WDT. v1.0 71M6521DE/71M6521FE Timer 1 Mode 0 Mode 1 YES ...
Page 28
... Note: The remaining bits in the IEN1 register are not used for watchdog control Interrupt Priority 0 Register (IP0): MSB -- WDTS Page 101 71M6521DE/71M6521FE ET2 ES0 ET1 EX1 Table 27: The IEN0 Register (see also Table 32) Table 28: The IEN0 Bit Functions (see also Table 32) ...
Page 29
... SFRs IEN0, IEN1, and IEN2. External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6521DE/FE, for example the CE, DIO, RTC EEPROM interface. Interrupt Overview When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 53. Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction, " ...
Page 30
... MSB SWDT Bit IEN1.7 IEN1.6 IEN1.5 IEN1.4 IEN1.3 IEN1.2 IEN1.1 IEN1.0 Page 101 71M6521DE/71M6521FE ES0 ET1 Table 35: The IEN0 Register Symbol Function EAL=0 – disable all interrupts EAL Not used for interrupt control WDT - ES0=0 – disable serial channel 0 interrupt ES0 ET1=0 – ...
Page 31
... Polarity control for INT3 falling edge, 1 – rising edge T2CON.6 I3FR Polarity control for INT3 falling edge, 1 – rising edge T2CON.5 I2FR Not used TCON.4 … -- T2CON0 v1.0 71M6521DE/71M6521FE - - - Table 39: The IEN2 Register Table 40: The IEN2 Bit Functions TF0 TR0 IE1 Table 41: The TCON Register Table 42: The TCON Bit Functions Table 43: The T2CON Bit Functions © ...
Page 32
... T0ACK and T1ACK – port ISR – active high when the service routine is called). External Interrupts The 71M6521DE/FE MPU allows seven external interrupts. These are connected as shown in Table 46. The direction of interrupts 2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupt 4 through 6 are defined as rising edge sensitive ...
Page 33
... MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 47), and these interrupts must be cleared by the MPU software. v1.0 71M6521DE/71M6521FE Interrupt Flag NAME LOCATION ...
Page 34
... OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 47) and these interrupts must be cleared by the MPU software. Interrupt Priority 0 Register (IP0) MSB -- WDTS Note: WDTS is not used for interrupt controls Interrupt Priority 1 Register (IP1) MSB - - Page 101 71M6521DE/71M6521FE Serial channel 1 interrupt - - - - - - Table 48: Priority Level Groups IP0.5 IP0.4 IP0.3 Table 49: The IP0 Register IP1 ...
Page 35
... Interrupt Request Flag IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 v1.0 71M6521DE/71M6521FE External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Table 52: Interrupt Polling Sequence ...
Page 36
... IE_PLLFALL UART0 EEPROM I2C XF ER_BUSY IE_XFER RTC_1S IE_RTC Page 101 71M6521DE/71M6521FE L ogi rru pt Polarity Control Select ion Reg IEN0.7 > IRCON IRCON.2 IRCON.3 > ...
Page 37
... Oscillator The 71M6521DE/FE oscillator drives a standard 32.768kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The 71M6521DE/FE oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. PLL and Internal Clocks Timing for the device is derived from the 32 ...
Page 38
... RAM, followed by a page erase. After this, the page can be updated in RAM and then written back to the flash memory. MPU RAM: The 71M6521DE/FE includes 2k-bytes of static RAM memory on-chip (XRAM) plus 256-bytes of internal RAM in the MPU core. The 2K-bytes of static RAM are used for data storage during normal MPU operations. ...
Page 39
... Table 55 shows the configuration for a DIO pin through its associated bit in its DIO_DIR register. Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in the Applications section and in the I/O RAM Description under LCD_NUM[4:0]. v1.0 71M6521DE/71M6521FE VARPULSE WPULSE DIO2 MOD ...
Page 40
... This limitation applies to any pin that can be configured as a LCD driver. The control resources selectable for the DIO pins are listed in Table 56. If more than one input is connected to the same resource, the resources are combined using a logical OR. Page 101 71M6521DE/71M6521FE ...
Page 41
... The LCD interface is flexible and can drive either digit segments or enunciator symbols. Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5Hz or 1Hz. The blink rate is controlled by LCD_Y. There can four pixels/segments connected to each of these drivers. LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0] identify which pixels, if any, are to blink. v1.0 71M6521DE/71M6521FE 71M6521 71M6521 3.3V 3.3V ...
Page 42
... Specification section for details regarding the ADC LSB size and the conversion accuracy. EEPROM Interface The 71M6521DE/FE provides hardware support for either type of EEPROM interface, a two-pin interface and a three-pin interface. The interfaces use the EECTRL and EEDATA registers for communication. Two-Pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices ...
Page 43
... SDATA output Z BUSY (bit) Figure 9: 3-Wire Interface. Write Command, HiZ=0. v1.0 71M6521DE/71M6521FE Description Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence ...
Page 44
... Figure 12: 3-Wire Interface. Write Command when CNT=0 EECTRL Byte Written Write -- With HiZ and WFR SCLK (output) SDATA (out/in) D7 SDATA output Z BUSY (bit) Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1. Page 101 71M6521DE/71M6521FE CNT Cycles (6 shown (LoZ) CNT Cycles (8 shown ...
Page 45
... Inadvertently setting this bit will inhibit access to the part via the ICE SECURE interface mechanism for actively resetting the part between reset and erase operations is provided (see ICE Interface description). v1.0 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 ...
Page 46
... Digital 0x19 Digital 0x1A Digital 0x1B Digital 0x1C 0X1D Digital 0X1E Digital 0X1F Digital Page 101 71M6521DE/71M6521FE Function DGND Reserved DGND Reserved VBIAS Not used -- Reserved -- Not used RTM (Real time output from CE) WDTR_EN (Comparator 1 Output AND V1LT3) Not used ...
Page 47
... Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the TERIDIAN 71M6521DE/FE functions by emulating the integral operation above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied with the time period of sampling will yield an accurate quantity for the momentary energy ...
Page 48
... THE PRECISE FREQUENCY 150*CRYSTAL FREQUENCY = 4.9152MHz. 3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES. Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers. Page 101 71M6521DE/71M6521FE System Timing Summary ADC MUX Frame Conversions, MUX_DIV=1 (4 conversions) is shown MUX_DIV ...
Page 49
... PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available (i.e. when V1<VBIAS), the 71M6521DE/FE can be in one of three battery modes, i.e. BROWNOUT, LCD, or SLEEP mode. As soon as V1 falls below VBIAS or when the part wakes up under battery power (with sufficient voltage margin), the part will automatically enter BROWNOUT mode (see Wake Up Behavior section) ...
Page 50
... While PLL_OK = 0, the I/O RAM bits ADC_E and CE_E are held in zero state disabling both ADC and CE. When PLL_OK falls, the CE program counter is cleared immediately and all FIR processing halts. Figure 19 shows the functional blocks active in BROWNOUT mode. Page 101 71M6521DE/71M6521FE System Power Battery Power (Non-volatile Supply) MISSION ...
Page 51
... In SLEEP mode, the battery current is minimized and only the Oscillator and RTC functions are active. This mode can be exited only by system power-up, a timeout of the wake-up timer push button event. Figure 21 shows the functional blocks active in SLEEP mode. v1.0 71M6521DE/71M6521FE MISSION V3P3SYS falls ...
Page 52
... OPT_RXDIS OPT_RXINV WPULSE/ OPT_TXMOD OPT_TXE VARPULSE OPT_FDC OPT_TXINV VBIAS POWER FAULT WAKE V1 COMP_STAT Figure 19: Functional Blocks in BROWNOUT Mode (inactive blocks grayed out) Page 101 71M6521DE/71M6521FE VREF ΔΣ ADC CONVERTER VBIAS VBIAS - V3P3A + ADC_E VREF VREF FIR_LEN MCK DIV CK32 ...
Page 53
... MOD DIO2/ OPT_RXDIS WPULSE/ OPT_RXINV OPT_TXMOD OPT_TXE VARPULSE OPT_FDC OPT_TXINV VBIAS POWER FAULT WAKE V1 COMP_STAT Figure 20: Functional Blocks in LCD Mode (inactive blocks grayed out) v1.0 71M6521DE/71M6521FE VREF ΔΣ ADC CONVERTER VBIAS VBIAS - V3P3A + ADC_E VREF VREF FIR_LEN MCK DIV CK32 PLL ...
Page 54
... OPT_RXDIS WPULSE/ OPT_RXINV OPT_TXMOD OPT_TXE VARPULSE OPT_FDC OPT_TXINV VBIAS POWER FAULT WAKE V1 COMP_STAT Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out) Page 101 71M6521DE/71M6521FE VREF ΔΣ ADC CONVERTER VBIAS VBIAS - V3P3A + ADC_E VREF VREF FIR_LEN MCK DIV CK32 ...
Page 55
... V3P3SYS and VBAT V1_OK Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together v1.0 71M6521DE/71M6521FE Transition MISSION 13..14 CK cycles Xtal 2048...4096 CK32 cycles BROWN- MISSION OUT Xtal 14.5 CK32 cycles 4096 CK32 ...
Page 56
... If system power is not present, the reset timer duration will be 2 cycles of the crystal clock, at which time the MPU will begin executing in BROWNOUT mode, starting at address 00. Power Fault Circuit: The 71M6521DE/FE includes a comparator to monitor system power fault conditions. When the output of the comparator falls (V1<VBIAS), the I/P RAM bits PLL_OK is zeroed and the part switches to BROWNOUT mode if a battery is present ...
Page 57
... Setting WAKE_ARM presets the timer with the values in WAKE_RES and WAKE_PRD and readies the timer to start when the MPU writes to SLEEP or LCD_ONLY. The timer is reset and disarmed whenever the MPU is awake. Thus desired to wake the MPU periodically (every 5 seconds, for example) the timer must be rearmed every time the MPU is awakened. v1.0 71M6521DE/71M6521FE Wake Up Behavior 15 CK32 cycles ...
Page 58
... SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals. VAR (DIO7) ADC Mux Ctrl. I/O RAM (CONFIGURATION RAM) Page 101 71M6521DE/71M6521FE Data Flow and V h for four-quadrant metering. These measurements are then accessed by the Pulses ...
Page 59
... APPLICATION INFORMATION Connection of Sensors (CT, Resistive Shunt) Figure 28 and Figure 29 show how resistive dividers, current transformers, and restive shunts are connected to the voltage and current inputs of the 71M6521DE/FE Vin * R /(R out out Figure 28: Resistive Voltage Divider (Left), Current Transformer (Right) v1 ...
Page 60
... GAIN _ ADJ In a production electricity meter, the 71M6521DE/FE is not the only component contributing to temperature dependency. A whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors) will contribute temperature effects. Since the output of the on-chip temperature sensor is accessible to the MPU, temperature-compensation mechanisms with great flexibility are possible ...
Page 61
... PPM deviations. A fairly close curve fit is achieved with the coefficients a = 10.89 0.122, and c = –0.00714 (see Figure 31). When applying the inverted coefficients, a curve (see Figure 31) will result that effectively neutralizes the original crystal characteristics. The frequencies were calculated using the fit coefficients as follows: v1.0 71M6521DE/71M6521FE Measured Nominal Frequency [Hz] +50 32767 ...
Page 62
... MAIN_EDGE_X address. This count is equivalent to twice the line frequency, and can be used to synchronize and/or correct the RTC. All digital input pins of the 71M6521DE/FE are compatible with external 5V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5V devices. ...
Page 63
... The 71M6521DE/FE has a LCD controller on-chip capable of controlling static or multiplexed LCDs. Figure 32 shows the basic connection for a LCD. The LCD segment pins can be organized in the following groups: 1. Nineteen pins are dedicated LCD segment pins (SEG0 to SEG18). 2. Four pins are dual-function pins CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32. ...
Page 64
... Note: LCD segment numbers are given without CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32. Table 62: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package Page 101 71M6521DE/71M6521FE Total Number of LCD Segment Pins DIO Pins in Addition Including SEG0- to DIO1-DIO2 SEG18 19 4-11,14-17, 19-21 20 ...
Page 65
... Pull-up resistors of roughly 10kΩ to V3P3D (to ensure operation in BROWNOUT mode) should be used for both SCL and SDA signals. The DIO_EEX register in I/O RAM must be set order to convert the DIO pins DIO4 and DIO5 to I and SDA v1.0 71M6521DE/71M6521FE Total Number of LCD DIO Pins in Addition Segment Pins In- ...
Page 66
... DI/DO signals, and the CS pin should be pulled down with a resistor to prevent that the three-wire device is selected on power-up, before the 71M6521DE/FE can establish a stable signal for CS. The DIO_EEX register in I/O RAM must be set order to convert the DIO pins DIO4 and DIO5 to uWire pins. The pull-up resistor for DIO5 may not be necessary. ...
Page 67
... For proper debugging or loading code into the 71M6521DE/FE mounted on a PCB necessary to have a provision like the header shown above R1 in Figure 37. A shorting jumper on this header pulls V3P3 disabling the hardware watchdog timer. ...
Page 68
... For a production meter, the RESET pin should be protected by the external components shown in Figure 38, right side. R should be in the range of 100Ω and mounted as closely as possible to the IC. 1 Since the 71M6521DE/FE generates its own power-on reset, a reset button or circuitry, as shown in Figure 38, left side, is only required for test units and prototypes. VBAT/ VBAT/ ...
Page 69
... Once the TERIDIAN 71M6521DE/FE energy meter device has been installed in a meter system, it has to be calibrated for tolerances of the current sensors, voltage dividers and signal conditioning components. The device can be calibrated using the gain and phase adjustment factors accessible to the CE ...
Page 70
... Not Used LCD0 2030 … … LCD19 2043 LCD24 2048 … … LCD38 2056 LCD_BLNK 205A LCD_BLKMAP19[3:0] Page 101 71M6521DE/71M6521FE I/O RAM MAP – In Numerical Order Bit 5 Bit 4 Bit 3 CE_E SUM_CYCLES[5:0] CHOP_E[1:0] RTM_E Not Used Reserved CKOUT_E[1:0] VREF_DIS ECK_DIS FIR_LEN ADC_E ...
Page 71
... IFLAGS E8 IE_PLLRISE IE_WAKE WD_RST Flash: ERASE 94 FLSHCTL B2 PREBOOT SECURE PGADR B7 Serial EEPROM: EEDATA 9E EECTRL Only available on QFN-68 package. Reserved in LQFP-64 package. v1.0 71M6521DE/71M6521FE RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] Bit 5 Bit 4 Bit 3 Reserved Reserved DIO_DIR0[7:4] Reserved Reserved * DIO2[5:3] (QFN-68) DIO_DIR2[5:3] (QFN-68) INT5 ...
Page 72
... DIO_R8[2:0] 200D[6:4] DIO_R9[2:0] 200E[2:0] DIO_R10[2:0] 200E[6:4] DIO_R11[2:0] SFRA2 DIO_DIR0[7:4,2:1] [7:4,2:0] Page 101 71M6521DE/71M6521FE Wk Dir Description 0 0 R/W Enables ADC and VREF. When disabled, removes bias current 0 - R/W Battery Measure Enable. When set, a load current is immediately applied to the battery and it is connected to the ADC to be measured on Alternative Mux Cycles ...
Page 73
... EX_XFR 2002[1] EX_RTC 2007[4] EX_FWCOL 2007[5] EX_PLL 2005[4] FIR_LEN v1.0 71M6521DE/71M6521FE 0 0 R/W Programs the direction of pins DIO15-DIO14, DIO11-DIO8. 1 indi- cates output. Ignored if the pin is not configured as I/ Programs the direction of pins DIO17-DIO16 (and DIO19-DIO21 for R/W the QFN package). 1 indicates output. Ignored if the pin is not con- figured as I/O ...
Page 74
... IE_PLLFALL SFRE8[0] IE_XFER SFRE8[1] IE_RTC SFRE8[5] IE_WAKE Page 101 71M6521DE/71M6521FE Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle. ...
Page 75
... LCD_SEG38[3:0] 2021[6] LCD_Y 2004[2:0] MPU_DIV[2:0] 2005[2] MUX_ALT 2002[7:6] MUX_DIV[1:0] v1.0 71M6521DE/71M6521FE -- -- R/W Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1 INT6. These bits do not have any memory and are primarily intended for debug use R/W Identifies which segments connected to SEG18 and SEG19 should blink. 1 means ‘ ...
Page 76
... RTC_MIN[5:0] 2017 RTC_HR[4:0] 2018 RTC_DAY[2:0] 2019 RTC_DATE[4:0] 201A RTC_MO[3:0] 201B RTC_YR[7:0] 201C[1] RTC_DEC_SEC 201C[0] RTC_INC_SEC 2002[3] RTM_E Page 101 71M6521DE/71M6521FE 0 0 R/W Selects OPT_TX modulation duty cycle OPT_FDC Function 00 50% Low 01 25% Low 10 12.5% Low 11 6.25% Low 0 0 R/W OPT_RX can be configured as an analog input to the optical UART comparator digital input/output, DIO1. 0— ...
Page 77
... VERSION[7:0] 2004[7] VREF_CAL 2004[3] VREF_DIS 20A9[7] WAKE_ARM 20A9[2:0] 001 WAKE_PRD 20A9[3] WAKE_RES v1.0 71M6521DE/71M6521FE 0 0 R/W Four RTM probes. Before each CE code pass, the values of these 0 0 registers are serially output on the RTM pin. The RTM registers are 0 0 ignored when RTM_E= ...
Page 78
... SFRE8[7] WD_RST 2002[2] WD_OVF 201F7:0] WE Page 101 71M6521DE/71M6521FE timer bit: Possible operations to this bit are: Read: Gets the status of the flag IE_PLLFALL Write 0: Clears the flag Write 1:.Resets the WDT 0 0 R/W The WD overflow status bit. This bit is set when the WD timer overflows ...
Page 79
... The required configuration is FIR_LEN = 1 (three cycles per conversion) and MUX_DIV = 1 (4 conversions per mux frame). v1.0 71M6521DE/71M6521FE CE Interface Description , where SAG_THR is the LSB value in the description of SAG_THR. ...
Page 80
... AC signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. CESTATUS represents the status flags for the preceding CE code pass (CE busy interrupt). Sag alarms are not remembered from one code pass to the next. The CE Status word is refreshed at every CE_BUSY interrupt. Page 101 71M6521DE/71M6521FE Element Input Mapping W0SUM/ W1SUM/ ...
Page 81
... MPU function. If EXT_PULSE = 1 and EQU = 0, the pulse inputs are W0SUM_X if I0SQSUM_X > I1SQSUM_X, and W1SUM_X, if I1SQSUM_X > I0SQSUM_X. Note: The 6521 Demo Code creep function halts both internal and external pulse generation. v1.0 71M6521DE/71M6521FE Default Description 0x5020 See description of CECONFIG below © ...
Page 82
... Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the integration time is 1 second. Additionally, the hardware will not permit output values to ‘fold back’ upon overflow. Page 101 71M6521DE/71M6521FE Default Description Number of consecutive voltage samples below SAG_THR before a sag 80 alarm is declared ...
Page 83
... MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal. MAINEDGE_X is the number of half- cycles accounted for in the last accumulated interval for the AC signal. TEMP_RAW may be used by the MPU to monitor chip temperature or to implement temperature compensation. v1.0 71M6521DE/71M6521FE -13 VMAX IMAX / In_8 Wh. -13 VMAX IMAX / In_8 Wh ...
Page 84
... RATE 46 2 where F = sampling frequency (2520.6Hz Pulse speed factor S Page 101 71M6521DE/71M6521FE Default Description The number of zero crossings of the selected voltage in the previous ac- N/A cumulation interval. Zero crossings are either direction and are debounced. N/A Filtered, unscaled reading from the temperature sensor. ...
Page 85
... QUANT_VARA 0x1B QUANT_VARB 0x16 QUANT_I v1.0 71M6521DE/71M6521FE CE Calibration Parameters Description These constants control the gain of their respective channels. The nominal value for each parameters is 2 proportional to its CAL parameter. Thus, if the gain of a channel is 1% slow, CAL should be scaled by 1/(1 – 0.01). These two constants control the CT phase compensation. No compensation occurs when PHADJ_X = 0 ...
Page 86
... Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. Page 101 71M6521DE/71M6521FE ABSOLUTE MAXIMUM RATINGS © 2005-2008 TERIDIAN Semiconductor Corporation ...
Page 87
... VBAT Operating Temperature Maximum input voltage on DIO/SEG pins configured as DIO input. * *Exceeding this limit will distort the LCD waveforms on other pins. v1.0 71M6521DE/71M6521FE FUNCTION Bypass capacitor for 3.3V supply Bypass capacitor for 3.3V output Bypass capacitor for V3P3SYS Bypass capacitor for V2P5 32.768kHz crystal – electrically similar to ECS ...
Page 88
... Hysteresis Current V1 Response Time V1 WDT Disable Threshold (V1-V3P3A) BATTERY MONITOR BME=1 PARAMETER Load Resistor LSB Value - does not include the 9-bit left shift at CE input. Offset Error Page 101 71M6521DE/71M6521FE PERFORMANCE SPECIFICATIONS CONDITION VIN=0V, ICE_E=1 VIN=V3P3D CONDITION I = 1mA LOAD I = 15mA LOAD I ...
Page 89
... Voltage overhead V3P3-V2P5 PSSR ΔV2P5/ΔV3P3 LOW POWER VOLTAGE REGULATOR Unless otherwise specified, V3P3SYS=V3P3A=0, PB=GND (BROWNOUT) PARAMETER V2P5 V2P5 load regulation VBAT voltage requirement PSRR ΔV2P5/ΔVBAT v1.0 71M6521DE/71M6521FE CONDITION CONDITION | I | ≤ 1mA V3P3D | I | ≤ 1mA V3P3D CONDITION Reduce V3P3 until V2P5 ...
Page 90
... Applies to all COM and SEG pins. PARAMETER VLC2 Max Voltage VLC1 Voltage, 1/3 bias ½ bias VLC0 Voltage, 1/3 bias ½ bias VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes. Page 101 71M6521DE/71M6521FE CONDITION Crystal connected CONDITION Ta = 22ºC VREF_CAL = 10µA, -10µA LOAD = + − ...
Page 91
... LSB values do not include the 9-bit left shift at CE input. †† measured at T during meter calibration and is stored in MPU or CE for use in temperature calculations v1.0 71M6521DE/71M6521FE CONDITION Vin = 200mV peak, 65Hz Vcrosstalk = largest measurement Vin=65Hz, 64kpts FFT, Blackman- ...
Page 92
... This spec is measured in production at the limits of the specified operating temperature. 4 This spec defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with other specs that use this nominal relationship as a reference. Page 101 71M6521DE/71M6521FE TIMING SPECIFICATIONS CONDITION CKMPU = 4.9MHz CKMPU = 1.25MHz ...
Page 93
... Harmonic Data - Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%. Figure 41: Meter Accuracy over Harmonics at 240V, 30A v1.0 71M6521DE/71M6521FE 1 10 Current [A] 60Hz Harmonic Data Harmonic © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC ...
Page 94
... Figure 42: Typical Meter Accuracy over Temperature Relative to 25°C 11.7 12.3 PIN No. 1 Indicator 0.60 Typ. NOTE: Controlling dimensions are in mm Page 101 71M6521DE/71M6521FE Relative Accuracy over Temperature -40 - Temperature [°C] PACKAGE OUTLINE (LQFP 64) 11.7 12.3 9.8 10.2 0.14 0.50 Typ. 0.28 © 2005-2008 TERIDIAN Semiconductor Corporation ...
Page 95
... Pin length is nominally 0.4mm (min. 0.3mm, max 0.4mm) **) Exposed pad is internally connected to GNDD. v1.0 71M6521DE/71M6521FE PACKAGE OUTLINE (QFN 68) Symbol θ © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 Dimensions (in mm): Min. Nom. ...
Page 96
... COM3 PINOUT (QFN 68 TERIDIAN 71M6521DE- © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 RESET ...
Page 97
... Note 2: Soldering of bottom internal pad is not required for proper operation. Note 3: The ‘y’ dimension has been elongated to allow for hand soldering and reworking. Production assembly may allow this dimension to be reduced as long as the ‘G’ dimension is maintained. v1.0 71M6521DE/71M6521FE Recommended PCB Land Pattern Dimensions Description e ...
Page 98
... See the crystal manufacturer datasheet for details. Pin types Power Output Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”. Page 101 71M6521DE/71M6521FE PIN DESCRIPTIONS © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC ...
Page 99
... Pin types Power Output Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified on the following page. v1.0 71M6521DE/71M6521FE Description LCD common outputs: These 4 pins provide the select signals for the LCD display. Dedicated LCD segment output pins. Multi-use pins, configurable as either LCD SEG driver or DIO. (DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface, WPULSE = DIO6, VARPULSE = DIO7 when configured as pulse outputs) ...
Page 100
... CMOS Output Output Pin GNDD GNDD Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output Page: 100 of 101 71M6521DE/71M6521FE LCD SEG LCD Output Driver Pin GNDD LCD Output Equivalent Circuit Type 5: LCD SEG or pin configured as LCD SEG V3P3A ...
Page 101
... Tape & Reel 32KB Bulk 32KB Tape & Reel © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 ORDERING PACKAGE NUMBER MARKING 71M6521DE-IGT/F 71M6521DE-IGT 71M6521DE-IGTR/F 71M6521DE-IGT 71M6521FE-IGT/F 71M6521FE-IGT 71M6521FE-IGTR/F 71M6521FE-IGT 71M6521DE-IM/F 71M6521DE-IM 71M6521DE-IMR/F 71M6521DE-IM 71M6521FE-IM/F 71M6521FE-IM 71M6521FE-IMR/F 71M6521FE-IM 1/18/2008 Page: 101 of 101 ...