ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet
ISPPAC-CLK5610V-01T100C
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ISPPAC-CLK5610V-01T100C Summary of contents
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November 2004 Features ■ 10MHz to 320MHz Input/Output Operation ■ Low Output to Output Skew (<50ps) ■ Low Jitter Peak-to-Peak (<60ps) ■ Programmable Fan-out Buffers • Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, ...
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Lattice Semiconductor General Description and Overview The ispClock5610 and ispClock5620 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5610 provides sin- gle-ended or five differential clock outputs, while ...
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Lattice Semiconductor Figure 2. ispClock5620 Functional Block Diagram PS0 PS1 Profile Select Control REFSEL REFA+ INPUT REFA- DIVIDER 0 M REFVTT (1-32) 1 REFB+ REFB- FEEDBACK N DIVIDER (1-32) FBKSEL FBKA+ E FBKA- 0 FBKVTT 1 ...
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Lattice Semiconductor Absolute Maximum Ratings Core Supply Voltage ...
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Lattice Semiconductor Performance Characteristics – Power Supply Symbol Parameter I Core Supply Current CCD I Analog Supply Current CCA Output Driver Supply Current I CCO (per Bank) I JTAG I/O Supply Current (static) CCJ 1. Supply current consumed by each ...
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Lattice Semiconductor DC Electrical Characteristics – Differential LVPECL Symbol Parameter V Input Voltage High IH V Input Voltage Low Output High Voltage Output Low Voltage OL 1. 100Ω differential termination. DC Electrical Characteristics – ...
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Lattice Semiconductor Switching Characteristics – Timing Adders for I/O Modes Adder Type 2 t Input Adders IOI LVTTL_in Using LVTTL Standard LVCMOS18_in Using LVCMOS 1.8V Standard LVCMOS25_in Using LVCMOS 2.5V Standard LVCMOS33_in Using LVCMOS 3.3V Standard SSTL2_in Using SSTL2 Standard ...
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Lattice Semiconductor Output Test Loads Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other selected parameters as noted in the various tables of this data sheet. Figure 3. CMOS Termination Load ispCLOCK ...
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Lattice Semiconductor Programmable Input and Output Termination Characteristics Symbol Parameter R Input Resistance IN R Output Resistance OUT Conditions Rin=40Ω setting Rin=45Ω setting Rin=50Ω setting Rin=55Ω setting Rin=60Ω setting Rin=65Ω setting Rin=70Ω setting Rout≈20Ω setting, VCCO=1.5V Rout≈20Ω setting, VCCO=1.8V Rout≈20Ω ...
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Lattice Semiconductor Performance Characteristics – PLL Symbol Parameter Reference and feedback input f f REF, FBK frequency range t Reference and feedback input CLOCKHI, t clock HIGH and LOW times CLOCKLO t Reference and feedback input RINP, t rise and ...
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Lattice Semiconductor Timing Specifications Skew Matching Symbol Parameter t Output-output Skew SKEW Programmable Skew Control Symbol Parameter t Skew Control Range SKRANGE SK Skew Steps per range STEPS 2 t Skew Step Size SKSTEP 3 t Skew Time Error SKERR ...
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Lattice Semiconductor Timing Specifications (Cont.) Boundary Scan Logic Symbol t TCK (BSCAN Test) Clock Cycle BTCP t TCK (BSCAN Test) Pulse Width High BTCH t TCK (BSCAN Test) Pulse Width Low BTCL t TCK (BSCAN Test) Setup Time BTSU t ...
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Lattice Semiconductor Timing Diagrams Figure 7. Erase (User Erase or Erase All) Timing Diagram VIH TMS VIL SU1 SU1 CKH GKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 8. Programming Timing Diagram VIH ...
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Lattice Semiconductor Typical Performance Characteristics I vs. f CCD (Normalized to 640MHz) 1.2 1 0.8 0.6 0.4 0.2 0 300 400 500 f (MHz) VCO Typical Skew Error vs. Setting (Skew Mode = FINE, f 100 ...
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Lattice Semiconductor match. The option of which mode to use is programmable and may be set using PAC-Designer software (available from the Lattice web site at www.latticesemi.com). In phase-lock mode the lock detector asserts the LOCK signal as soon as ...
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Lattice Semiconductor Table 2. PAC-Designer Recommended Loop Filter Settings Note that the choice of loop filter parameters can have significant effects on settling time, output jitter, and whether the PLL will be fundamentally stable and be able to lock to ...
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Lattice Semiconductor M, N, and V Dividers The ispClock5600 incorporates a set of programmable dividers which provide the ability to synthesize output fre- quencies differing from that of the reference clock input. The input divider prescales the input ...
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Lattice Semiconductor Table 3. Nominal Output Duty Cycle vs. V-Divider Setting PLL_BYPASS Mode The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without using the PLL functions. When PLL_BYPASS mode is enabled ...
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Lattice Semiconductor Table 4. REFSEL and FBKSEL Operation for ispClock5620 REFSEL • LVTTL (3.3V) • LVCMOS (1.8V, 2.5V, 3.3V) • SSTL2 • SSTL3 • HSTL • Differential SSTL2 • Differential SSTL3 • Differential HSTL • LVDS • LVPECL (differential, 3.3V) ...
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Lattice Semiconductor Figure 14. LVCMOS/LVTTL Input Receiver Configuration Signal In No Connect No Connect HSTL, SSTL2, SSTL3 The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input pair. ...
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Lattice Semiconductor Differential HSTL and SSTL HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory systems. Figure 16 shows how ispClock5600 reference input should be configured for accepting these standards. The major ...
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Lattice Semiconductor Note that while a floating 100Ω resistor forms a complete termination for an LVDS signal line, additional circuitry may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out- put driver ...
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Lattice Semiconductor In the case where an output bank is unused, the associated VCCO pin may be either left floating or tied to ground to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ...
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Lattice Semiconductor end, the ispClock5600’s internal termination resistors are not available in these modes. Also note that output slew- rate control is not available in LVDS or LVPECL mode, and that these drivers always operate at a fixed slew-rate. Polarity ...
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Lattice Semiconductor LVPECL mode. The far end of the transmission line must be terminated with a 100Ω resistor across the two signal lines. Figure 22. Configuration for LVDS and LVPECL Output Modes LVDS/LVPECL mode ispClock5600 Note that when in LVPECL ...
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Lattice Semiconductor Figure 23. Maximum Ambient Temperature vs. Number of Active Output Banks Temperature Derating Curves (Outputs LVCMOS 3.3V Active Output Banks Temperature Derating Curves (Outputs LVDS ...
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Lattice Semiconductor sumption by turning off unused drivers, these features can also be used for functional testing purposes. The follow- ing inputs pins are used for output enable functions: • GOE – global output enable • OEX, OEY – secondary ...
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Lattice Semiconductor Unlike the skew adjustment features provided in many competing products, the ispClock5600’s skew adjustment feature provides exact and repeatable delays which exhibit extremely low channel-to-channel and device-to-device variation. This is achieved by deriving all skew timing from the ...
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Lattice Semiconductor which are multiples of four (in fine mode) may be divided by two. For example, a V-divider setting of 24 will divide down to 12, which is also a legal V-divider setting, whereas an initial setting of 26 ...
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Lattice Semiconductor Figure 26. Output Timing Adders for Logic Type (a) and Output Slew Rate (b) LVPECL Output ( IOS LVTTL Output (T = 0.1ns) IOS Similarly, when one changes the slew rate of an output, the output ...
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Lattice Semiconductor Profile Select The ispClock5600 stores all internal configuration data in on-board E figuration profiles may be stored in each device. The choice of which configuration profi active is specified thought the profile select inputs PS0 ...
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Lattice Semiconductor When the ispClock5600 begins operating from initial power-on, the VCO starts running at a very low frequency (<100 MHz) which gradually increases as it approaches a locked condition. To prevent invalid outputs from being applied to the rest ...
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Lattice Semiconductor User Electronic Signature A user electronic signature (UES) feature is included in the E 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control data. The ...
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Lattice Semiconductor IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the ispClock5600 is facilitated via an IEEE 1149.1 test access port (TAP used by the ispClock5600 both as a serial programming interface, and for boundary ...
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Lattice Semiconductor Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by ...
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Lattice Semiconductor facturer to determine. The instruction word length is not mandated other than minimum of two bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- ...
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Lattice Semiconductor scan operation, after power-up of the device issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 8. Figure 32. ispClock5600 Family ID Codes Version (4 bits) 2 ...
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Lattice Semiconductor VERIFY – This instruction loads data from the E shifted out. The device must already be in programming mode for this instruction to execute. VERIFY_INCR – This instruction copies the E umn register and then auto-increments the value ...
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Lattice Semiconductor Pin Descriptions Pin Name Description VCCO_0 Output Driver ‘0’ VCC VCCO_1 Output Driver ‘1’ VCC VCCO_2 Output Driver ‘2’ VCC VCCO_3 Output Driver ‘3’ VCC VCCO_4 Output Driver ‘4’ VCC VCCO_5 Output Driver ‘5’ VCC VCCO_6 Output Driver ...
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Lattice Semiconductor Pin Descriptions (Continued) Pin Name Description VCCD Digital Core VCC GNDD Digital GND VCCJ JTAG interface VCC REFA+ Clock Reference A positive input REFA- Clock Reference A negative input REFB+ Clock Reference B positive input REFB- Clock Reference ...
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Lattice Semiconductor Detailed Pin Descriptions VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should ...
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Lattice Semiconductor GOE – Global output enable. This pin drives all outputs to a high-impedance state when it is pulled HIGH. GOE also controls the internal feedback buffer, so that bringing GOE high will cause the PLL to lose lock. ...
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Lattice Semiconductor Package Diagrams 48-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR 0. SECTION NOTES: 1. DIMENSIONING ...
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Lattice Semiconductor 100-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR TOP VIEW SECTION B-B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL ...
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... Lattice Semiconductor Part Number Description ispPAC-CLK56XX XXXX X Device Family Device Number CLK5610 CLK5620 Ordering Information Conventional Packaging Part Number ispPAC-CLK5610V-01T48C ispPAC-CLK5620V-01T100C Part Number ispPAC-CLK5610V-01T48I ispPAC-CLK5620V-01T100I Lead-Free Packaging Part Number ispPAC-CLK5610V-01TN48C ispPAC-CLK5620V-01TN100C Part Number ispPAC-CLK5610V-01TN48I ispPAC-CLK5620V-01TN100I Commercial Clock Outputs Supply Voltage 10 3 ...
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... Lattice Semiconductor Package Options ispClock5610: 48-pin TQFP VCCO_0 BANK_0B BANK_0A GNDO_0 VCCO_1 BANK_1B BANK_1A GNDO_1 VCCO_2 BANK_2B BANK_2A GNDO_2 ispPAC CLK5610V-01T48C ispClock5600 Family Data Sheet 36 VCCJ 35 TDO 34 LOCK 33 VCCD 32 GNDO_4 31 BANK_4A 30 BANK_4B 29 VCCO_4 28 GNDO_3 27 BANK_3A ...
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... VCCO_1 7 BANK_1B 8 BANK_1A 9 GNDO_1 10 VCCO_2 11 BANK_2B 12 BANK_2A 13 GNDO_2 14 VCCO_3 15 BANK_3B 16 BANK_3A 17 GNDO_3 18 VCCO_4 19 BANK_4B 20 BANK_4A 21 GNDO_4 22 23 n/c n/c 24 n/c 25 ispPAC-CLK5620V-01T100C 47 ispClock5600 Family Data Sheet 75 n/c 74 VCCJ 73 TDO 72 LOCK 71 VCCD 70 GNDO_9 69 BANK_9A 68 BANK_9B 67 VCCO_9 66 GNDO_8 65 BANK_8A 64 BANK_8B 63 VCCO_8 62 GNDO_7 61 BANK_7A 60 BANK_7B 59 VCCO_7 58 GNDO_6 ...