ISPPAC-POWR60401TE LATTICE [Lattice Semiconductor], ISPPAC-POWR60401TE Datasheet
ISPPAC-POWR60401TE
Related parts for ISPPAC-POWR60401TE
ISPPAC-POWR60401TE Summary of contents
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... The ispPAC- POWR604 device has the capability to be configured through software to control up to four outputs for power supply sequencing and six comparators monitoring sup- ply voltage limits, along with four digital inputs for inter- facing to other control circuits or digital logic ...
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... The ispPAC-POWR604 device contains an internal PLD that is programmable by the user to implement digi- tal logic functions and control state machines. The internal PLD connects to two programmable timers, special purpose I/O and the programmable monitoring circuit blocks ...
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... Analog Input 36 VMON5 Analog Input 37 VMON6 Analog Input 38 NC — 39 CREF Reference 40 NC — — ispPAC-POWR604 Data Sheet Voltage Range — No Connect — No Connect — No Connect — No Connect 2.25V-5.5V Main Power Supply 1, 3 VDDINP Input VDDINP Input VDDINP ...
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... PLD inputs and outputs can be used to generate these signals. The RESET connected to the POR pin can be used if multiple ispPAC-POWR604 devices are cascaded together in expansion mode manual reset button is needed to reset the PLD logic to the initial state. While using the ispPAC-POWR604 in hot-swap applications it is recommended that either the RESET pin be connected to the POR pin, or connect a capacitor to ground (such that the time constant with the pull-up resistor) from the RESET pin ...
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... APROG programming T Ambient temperature A 1. The ispPAC-POWR604 device must be powered from 3.0V to 5.5V during programming of the the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V DDINP supply voltge for the given input logic range. ...
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... Internal Osc 250kHz External clock applied Internal Osc 250kHz Over Recommended Operating Conditions Conditions 0V ≤ V ≤ DDINP 25 °C 25 ° 4mA SINKOUT (Note 1) (Note 1) SINKTOTAL 2-6 ispPAC-POWR604 Data Sheet Min. Typ. Max. 1 — — 1.15 1 — — 2.1 Min. Typ. Max. — 100mV TRIP — ...
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... Note: All the above parameters apply to signal paths from the digital inputs [IN1-IN4]. V (V) IL Min. Max. -0.3 0.8 -0.3 0.7 Over Recommended Operating Conditions Conditions Applied to IN1-IN4 Stable input before clock edge (Note 1) Data valid before clock (Note 1) Hold data after clock . DD 2-7 ispPAC-POWR604 Data Sheet V (V) IH Min. Max. 2.0 5.5 1.7 5.5 Min. Typ. Max. Units 20 300 µs ns µ ...
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... DIH DOZH DOV t DO Conditions 1 2 CMOS cells. t CKMIN MSS Program and Erase cycles DOXZ 2-8 ispPAC-POWR604 Data Sheet Min Typ. Max 1 200 200 200 200 200 40 40 100 40 100 t t PWP, PWE t MSS executed in Run-Test/Idle Units µ ...
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... Typical V Comparator Trip Point MON Accuracy vs. Temperature - Temperature (°C) 2-9 ispPAC-POWR604 Data Sheet Propagation Delay vs. Overdrive Glitch Filter = 20μs Glitch Filter = 5μ 100 Input Overdrive (mV) inputs to outputs MON 100 150 200 ...
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... Each of the six comparators are independently set in the same way. Theory Of Operation The ispPAC-POWR604 incorporates programmable voltage monitors along with digital inputs and outputs. The eight macrocell PLD inputs are from the six voltage monitors and four digital inputs. There are two embedded pro- grammable timers that interface with the PLD, along with an internal programmable oscillator ...
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... PLD Architecture The ispPAC-POWR604 digital logic is composed of an internal PLD that is programmed to perform the sequencing functions. The PLD architecture allows flexibility in designing various state machines and control logic used for monitoring ...
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... The macrocell also supports asynchronous reset and preset functions, derived from product terms, the global reset input, or the power-on reset signal. Figure 2-3. ispPAC-POWR604 Macrocell Block Diagram Global Polarity Fuse for Block Init Product-Term ...
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... Figure 2-4. PLD and Timer Functional Block Diagram POR/RESET 6 VMON[1:6] Comparators 4 IN[1: Timer1 Timer2 MC0 MC1 MC2 AND MC3 ARRAY MC4 20 Inputs 41 PT MC5 8 Outputs MC6 MC7 BLK-INIT PT 8 Routing Pool Clock Generation 2-13 ispPAC-POWR604 Data Sheet OUT5 OUT6 Output Routing OUT7 Pool OUT8 ...
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... Lattice Semiconductor Clock and Timer Systems Figure 2-5 shows a block diagram of the ispPAC-POWR604’s internal clock and timer systems. The PLD clock can be programmed with eight different frequencies based on the internal oscillator frequency of 250kHz. Figure 2-5. Clock and Timer Block Internal OSC 250kHz CLK Table 2-2 ...
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... Timer Period Timer Reset Expired Timer ProgrammableTimer Delay 2-15 ispPAC-POWR604 Data Sheet ÷ ÷ ÷ ÷ 128 ÷ ÷ ÷ ÷ 256 2 kHz 1 kHz 0.5 kHz 1.024 ms 2.048ms 2.048ms 4.096 ms 4.096 ms 4.096 ms 8.192 ms 8.192 ms 8.192 ms 16.384 ms 16 ...
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... The optional identification (IDCODE) register described in IEEE 1149.1 is also included in the ispPAC-POWR604. Six additional user data registers are included in the TAP of the ispPAC-POWR604 as shown in Figure 2-7. Most of these additional registers are used to program and verify the analog configuration (CFG) and PLD bits. A status register is also provided to read the status of the six analog comparators ...
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... UES REGISTER (16 bits) CFG REGISTER (17 bits) CFG ADDRESS REGISTER (4 bits) PLD DATA REGISTER (41 bits) PLD ADDRESS REGISTER (43 bits) INSTRUCTION REGISTER (6 bits) BYPASS REGISTER (1 bit) TEST ACCESS PORT (TAP) LOGIC TCK TMS 2-17 ispPAC-POWR604 Data Sheet ANALOG CONFIGURATION 2 E NON-VOLATILE MEMORY (68 bits) PLD AND / ARCH E 2 ...
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... BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- tively). The ispPAC-POWR604 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured, verified, and monitored ...
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... BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC- POWR604. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). ...
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... ADDPLD instruction. This instruction also forces the outputs into the SAF- ESTATE. DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ispPAC-POWR604 for a read cycle. This instruction also forces the outputs into the SAFESTATE. Part Number ...
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... This instruction is effective after Update-Instruction-Register JTAG state. PROGRAMEN – This instruction enables the programming mode of the ispPAC-POWR604. This instruction also forces the outputs into the SAFESTATE. IDCODE – This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO (Figure 2-10), to support reading out the identifi ...
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... Application Example The ispPAC-POWR604 device has six comparators to monitor various power supply levels. The comparators each have a programmable trip point that is programmed by the user at design time. The output of the comparators feed into the PLD logic array to drive the state machine logic or monitor logic. The outputs of comparators COMP1 ...
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... Lattice Semiconductor Figure 2-13. Typical Application Example: ispPAC-POWR604 Interfacing to CPU Board Using Four Outputs, Four Inputs and Six VMON Voltage Monitoring Signals Voltage Monitor 6 Voltage Monitor 5 6 Analog Inputs VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 ispPAC-POWR604 V DD CLK RESET CARD_RESETN IN1 WDT_IN ...
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... PAC-Designer. PAC-Designer has an easy-to-use graphical user interface (Figure 2-14) that allows the user to set up the ispPAC-POWR604 to perform required functions, such as timed sequences for power supply or moni- tor trip points for the voltage monitor inputs. The software tool gives the user control over how the device drives the outputs and the functional confi ...
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... TAP interface and shifts in the JEDEC data bits that set the configuration of all the analog and digital circuitry that the user has defined during the design process. Power to the device must be set at 3.0V to 5.5V during programming, once the programming steps have been com- pleted, the power supply to the ispPAC-POWR604 can be set from 2.25V to 5V. Once programmed, the on-chip 2 non-volatile E CMOS bits hold the entire design confi ...
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... The User Electronic Signature (UES), allows the designer to include identification bits or serial numbers inside the 2 device, stored in E CMOS memory. The ispPAC-POWR604 contains 16 UES bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control codes. Electronic Security An Electronic Security Fuse (ESF) bit is provided to prevent unauthorized readout of the E programmed, this cell prevents further access to the functional user bits in the device ...
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... A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. 0. 0.20 H A-B SEE DETAIL 'A' C LEAD FINISH 0. BASE METAL 2-27 ispPAC-POWR604 Data Sheet 44X BOTTOM VIEW 0.20 MIN. A1 1.00 REF. DETAIL 'A' SYMBOL MIN. NOM 0. ...
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... Lattice Semiconductor Part Number Description ispPAC-POWR604 - 01XX44X Device Family Device Number ispPAC-POWR604 Ordering Information Conventional Packaging ispPAC-POWR604-01T44I ispPAC-POWR604-01T44E Lead-Free Packaging ispPAC-POWR604-01TN44I ispPAC-POWR604-01TN44E Industrial Part Number Package TQFP Automotive Part Number Package TQFP Lead-Free Industrial Part Number Package TQFP Lead-Free Automotive Part Number ...
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... Automotive part number added in the Ordering Information section. 02.0 Ordering Part Number added for Lead Free packaging, Ordering Infor- mation section. 02.1 Add R/C network to RESET pin in Application Block Diagram to acco- modate hot-swapping. Edited note 6 in Pin Descriptions table to support hot-swapping. 2-29 ispPAC-POWR604 Data Sheet VMON2 33 VMON1 32 TMS 31 TDI 30 ...