GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 78
![no-image](/images/no-image-200.jpg)
GS4910B
Manufacturer Part Number
GS4910B
Description
HD/SD/Graphics Clock and Timing Generator with GENLOCK
Manufacturer
GENNUM [Gennum Corporation]
Datasheet
1.GS4910B.pdf
(113 pages)
- Current page: 78 of 113
- Download datasheet (2Mb)
SDOUT
SCLK
SDIN
CS
SDOUT
SCLK
SDIN
CS
R/W
R/W
R/W
R/W
t
0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
t
3
AutoInc
AutoInc
t
AutoInc
AutoInc
1
A11
A11
A11
A11
A10
A10
A10
A10
t
2
A9
A9
A9
A9
A8
A8
A8
A8
A7
A7
A7
A7
t
Table 3-12: GSPI Timing Parameters
Figure 3-17: GSPI Read Mode Timing
Figure 3-18: GSPI Write Mode Timing
36655 - 2
8
Parameter
A6
A6
A6
A6
A5
A5
A5
A5
t
t
t
t
t
t
t
t
t
0
1
2
3
4
5
6
7
8
A4
A4
A4
A4
A3
A3
A3
A3
April 2006
A2
A2
A2
A2
Definition
The minimum duration of time chip select, CS, must be
LOW before the first SCLK rising edge.
The minimum SCLK period.
Duty cycle tolerated by SCLK.
Minimum input setup time.
The minimum duration of time between the last SCLK
command word (or data word if the Auto-Increment bit is
HIGH) and the first SCLK of the data word (write cycle).
The minimum duration of time between the last SCLK
command word (or data word if the Auto-Increment bit is
HIGH) and the first SCLK of the data word (read cycle).
Minimum output hold time (15pF load).
The minimum duration of time between the last SCLK of
the GSPI transaction and when CS can be set HIGH.
Minimum input hold time.
A1
A1
A1
A1
A0
A0
A0
A0
t
t
5
4
D15
D15
D15
D14
D14
D14
D13
D13
t
6
D13
D12
D12
D12
GS4911B/GS4910B Data Sheet
D11
D11
D11
D10
D10
D10
D9
D9
D9
D8
D8
D8
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
Specification
1.5 ns
40% to 60%
1.5 ns
37.1 ns
148.4 ns
1.5 ns
37.1 ns
1.5 ns
100 ns
D4
D3
D3
D3
D2
D2
D2
78 of 113
D1
D1
D1
D0
D0
D0
t
7
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