GAL20LV8D-7LJ LATTICE [Lattice Semiconductor], GAL20LV8D-7LJ Datasheet - Page 15

• Manufacturer Part Number: GAL20LV8D-7LJ
• Description: Low Voltage E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

Circuitry within the GAL20LV8D provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q outputs
set low after a specified time (
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. Because of the asynchro-
nous nature of system power-up, some conditions must be met to
Typ. Vref = Vcc
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Typical Input
FEEDBACK/EXTERNAL
INTERNAL REGISTER
OUTPUT REGISTER
Active Pull-up
Circuit
t
pr, 1 s MAX). As a result, the state
Vref
Q - OUTPUT
CLK
Vcc
Vcc
Vcc (min.)
Vcc
15
t
pr
provide a valid power-up reset of the device. First, the V
be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will re-
set within a maximum of
avoid clocking the device until all input and feedback path setup
times have been met. The clock must also meet the minimum pulse
width requirements.
Typ. Vref = Vcc
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Specifications GAL20LV8
Tri-State
Control
t
wl
Feedback
t
su
t
Typical Output
pr time. As in normal system operation,
Vcc
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
CC
PIN
PIN
rise must