GAL20V8B-10LJI LATTICE [Lattice Semiconductor], GAL20V8B-10LJI Datasheet

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GAL20V8B-10LJI

Manufacturer Part Number
GAL20V8B-10LJI
Description
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
• HIGH PERFORMANCE E
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
• ACTIVE PULL-UPS ON ALL PINS
• E
• EIGHT OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
The GAL20V8C, at 5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL20V8 are the PAL architectures listed
in the table of the macrocell description section. GAL20V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20v8_07
Features
Description
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 24-pin PAL
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
Fuse Map/Parametric Compatibility
2
) floating gate technology to provide the highest speed
®
Advanced CMOS Technology
2
CMOS
®
Devices with Full Function/
®
TECHNOLOGY
1
Functional Block Diagram
Pin Configuration
I/CLK
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
11
5
7
9
12
4
GAL20V8
Top View
2
14
PLCC
High Performance E
28
16
26
18
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
Generic Array Logic™
GAL20V8
I/CLK
GND
8
8
8
8
8
8
8
8
IMUX
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
IMUX
I
I
I
I
I
I
I
I
I
I
1
12
6
OE
2
20V8
GAL
DIP
CLK
CMOS PLD
August 2006
24
18
13
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
Vcc
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
I

Related parts for GAL20V8B-10LJI

GAL20V8B-10LJI Summary of contents

Page 1

Features • HIGH PERFORMANCE E 2 CMOS ® TECHNOLOGY — Maximum Propagation Delay — Fmax = 166 MHz — Maximum from Clock Input to Data Output ® — UltraMOS Advanced CMOS Technology • 50% to 75% ...

Page 2

GAL20V8 Ordering Information Conventional Packaging Commercial Grade Specifications ...

Page 3

... Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory. Part Number Description XXXXXXXX GAL20V8C Device Name GAL20V8B Speed (ns Low Power Power Q = Quarter Power ...

Page 4

Output Logic Macrocell (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. There are three global OLMC ...

Page 5

Registered Mode In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 20R8 and 20RP4 devices with various permutations of polarity, I/O and register ...

Page 6

Registered Mode Logic Diagram 1(2) 0 2(3) 0000 0280 3(4) 0320 0600 4(5) 0640 0920 5(6) 0960 1240 6(7) 1280 1560 7(9) 1600 1880 8(10) 1920 2200 9(11) 2240 2520 10(12) 11(13) DIP (PLCC) Package Pinouts 2640 ...

Page 7

Complex Mode In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 20L8 and 20P8 devices with programmable polarity in each macrocell six I/Os ...

Page 8

Complex Mode Logic Diagram 1(2) 0 2(3) 0000 0280 3(4) 0320 0600 4(5) 0640 0920 5(6) 0960 1240 6(7) 1280 1560 7(9) 1600 1880 8(10) 1920 2200 9(11) 2240 2520 10(12) 11(13) Specifications GAL20V8 DIP (PLCC) Package Pinouts 2640 4 ...

Page 9

Simple Mode In the Simple mode, pins are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 14L8 and 16P6 devices with many permutations of ge- neric ...

Page 10

Simple Mode Logic Diagram 1( 2(3) 0000 0280 3(4) 0320 0600 4(5) 0640 0920 5(6) 0960 1240 6(7) 1280 1560 7(9) 1600 1880 8(10) 1920 2200 9(11) 2240 2520 10(12) 11(13) DIP (PLCC) Package Pinouts 2640 8 12 ...

Page 11

Absolute Maximum Ratings Supply voltage V ...................................... –0.5 to +7V CC Input voltage applied .......................... –2 Off-state output voltage applied ......... –2 Storage Temperature ................................ –65 to 150°C Ambient Temperature with Power Applied ........................................ –55 to ...

Page 12

AC Switching Characteristics TEST DESCRIPTION PARAMETER 1 COND . Input or I/O to Comb. Output Clock to Output Delay — Clock to Feedback Delay t su — Setup Time, Input or ...

Page 13

... The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A Specifications GAL20V8B Recommended Operating Conditions (1) Commercial Devices: +1.0V ...

Page 14

... Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Capacitance ( ° 1.0 MHz) SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL20V8B Specifications GAL20V8 Over Recommended Operating Conditions COM COM / IND -7 -10 MIN. MAX. MIN. MAX — ...

Page 15

Switching Waveforms INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width Specifications GAL20V8 INPUT or I/O FEEDBACK ...

Page 16

... Input Rise and GAL20V8B Fall Times GAL20V8C Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GAL20V8B Output Load Conditions (see figure) Test Condition 200Ω B Active High ∞ Active Low 200Ω ...

Page 17

Electronic Signature An electronic signature is provided in every GAL20V8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always ...

Page 18

Power-Up Reset INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL20V8 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set t low after a specified time ( pr, ...

Page 19

GAL20V8C: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 ...

Page 20

GAL20V8C: Typical AC and DC Characteristic Diagrams Vol vs Iol 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta ...

Page 21

... GAL20V8B-7/-10: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 Temperature (deg. C) Delta Tpd Outputs 0 -0 Number of Outputs Switching Delta Tpd vs Output Loading Output Loading (pF) Normalized Tco vs Vcc 1.2 RISE 1.1 FALL 1 0 ...

Page 22

... GAL20V8B-7/-10: Typical AC and DC Characteristic Diagrams Vol vs Iol 1 0.75 0.5 0.25 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Specifications GAL20V8 Voh vs Ioh 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 -55 - 100 125 Temperature (deg. C) ...

Page 23

... GAL20V8B-15/-25: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0 Number of Outputs Switching Delta Tpd vs Output Loading 10 RISE 8 6 FALL ...

Page 24

... GAL20V8B-15/-25: Typical AC and DC Characteristic Diagrams Vol vs Iol 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Specifications GAL20V8 Voh vs Ioh 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 -55 - 100 125 Temperature (deg. C) ...

Page 25

Revision History Date Version - 20v8_06 August 2006 20v8_07 Specifications GAL20V8 Change Summary Previous Lattice release. Updated for lead-free package options. 25 ...

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