GAL16V8D-10QPN LATTICE [Lattice Semiconductor], GAL16V8D-10QPN Datasheet

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GAL16V8D-10QPN

Manufacturer Part Number
GAL16V8D-10QPN
Description
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet

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GAL16V8D-10QPN
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12 388
• HIGH PERFORMANCE E
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
• ACTIVE PULL-UPS ON ALL PINS
• E
• EIGHT OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
The GAL16V8, at 3.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL16V8 are the PAL architectures listed
in the table of the macrocell description section. GAL16V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
16v8_11
Features
Description
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.0 ns Maximum from Clock Input to Data Output
— UltraMOS
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 20-pin PAL
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
Function/Fuse Map/Parametric Compatibility
2
) floating gate technology to provide the highest speed
®
Advanced CMOS Technology
2
CMOS
®
Devices with Full
®
TECHNOLOGY
1
I/CLK
Functional Block Diagram
Pin Configuration
I
I
I
I/CLK
I
I
GND
I
I
I
I
I
I
I
I
4
6
8
I
I
I
I
I
I
I
I
I
9
I
GAL16V8
GND
1
5
10
Top View
2
I
PLCC
SOIC
16V8
GAL
View
Top
I/CLK
I/OE
11
High Performance E
Vcc
I/O/Q
20
20
11
15
I/O/Q
I/O/Q
13
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
18
14
16
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Generic Array Logic™
GAL16V8
8
8
8
8
8
8
8
8
I/CLK
GND
CLK
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I
I
I
I
I
I
I
I
5
1
10
2
OE
16V8
CMOS PLD
GAL
August 2006
DIP
20
11
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE

Related parts for GAL16V8D-10QPN

GAL16V8D-10QPN Summary of contents

Page 1

Features 2 ® • HIGH PERFORMANCE E CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.0 ns Maximum from Clock Input to Data Output — UltraMOS ® Advanced CMOS Technology • 50% to 75% ...

Page 2

GAL16V8 Ordering Information Conventional Packaging Commercial Grade Specifications ...

Page 3

... Part Number Description GAL16V8D Device Name Speed (ns Low Power Power Q = Quarter Power ...

Page 4

Output Logic Macrocell (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. There are three global OLMC ...

Page 5

Registered Mode In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register ...

Page 6

Registered Mode Logic Diagram 1 0 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 Specifications GAL16V8 DIP & PLCC Package Pinouts 2128 28 PTD ...

Page 7

Complex Mode In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell six I/O's ...

Page 8

Complex Mode Logic Diagram 1 0 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 Specifications GAL16V8 DIP & PLCC Package Pinouts 2128 4 8 ...

Page 9

Simple Mode In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of ge- neric ...

Page 10

Simple Mode Logic Diagram 1 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 Specifications GAL16V8 DIP & PLCC Package Pinouts 2128 ...

Page 11

... The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A Specifications GAL16V8D Recommended Operating Conditions (1) Commercial Devices: +1.0V ...

Page 12

... Refer to fmax Descriptions section. Characterized but not 100% tested. 4) Characterized but not 100% tested. Capacitance ( ° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL16V8D Over Recommended Operating Conditions MAXIMUM* UNITS COM COM COM / IND - UNITS MIN ...

Page 13

... Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance ( ° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL16V8D Specifications GAL16V8 Over Recommended Operating Conditions COM / IND -10 MIN. MAX — 6 7.5 — ...

Page 14

Switching Waveforms INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width INPUT or I/O FEEDBACK CLK VALID ...

Page 15

... Input Rise and Fall Times GAL16V8D-3/-5/-7 Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GAL16V8D (except -3) Output Load Conditions (see figure above) Test Condition 200Ω B Active High ∞ ...

Page 16

... Switching Test Conditions (Continued) GAL16V8D-3 Output Load Conditions (see figure at right) Test Condition A B High Z to Active High at 1.9V High Z to Active Low at 1.0V C Active High to High Z at 1.9V Active Low to High Z at 1.0V Electronic Signature An electronic signature is provided in every GAL16V8 device. It contains 64 bits of reprogrammable memory that can contain user defined data ...

Page 17

Power-Up Reset INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL16V8 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q t outputs set low after a specified time ( ...

Page 18

... GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams N ormalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 PT H->L PT L->H 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs Switching 0 -0.1 -0.2 -0.3 -0 Number of Outputs Switching Delta Tpd vs Output Loading RISE ...

Page 19

... GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams Vol vs Iol 1 0.75 0.5 0. Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta Icc vs Vin (1 input 0.5 1 1.5 2 2.5 3 3.5 4 Vin (V) Specifications GAL16V8 Voh vs Ioh Ioh (mA) Normalized Icc vs Temp 1 ...

Page 20

... GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.15 1.1 RISE FALL 1.05 1 0.95 0.9 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tpd vs Temp 1.3 RISE 1.2 FALL 1.1 1 0.9 0.8 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs Switching 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0 Number of Outputs Switching Delta Tpd vs Output Loading ...

Page 21

... GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams Vol vs Iol 0.5 0.4 0.3 0.2 0 Iol (mA) Normalized Icc vs Vcc 1.1 1 0.9 0.8 3 3.15 3.3 3.45 Supply Voltage (V) Delta Icc vs Vin (1 input 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Vin (V) Voh vs Ioh ...

Page 22

... GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 PT H->L PT L->H 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0.2 -0.4 -0.6 -0 Number of Outputs Switching Delta Tpd vs Output Loading 12 10 RISE 8 FALL ...

Page 23

... GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams Vol vs Iol 0.6 0.4 0 Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta Icc vs Vin (1 input 0.5 1 1.5 2 2.5 3 3.5 Vin (V) Voh vs Ioh Ioh (mA) Normalized Icc vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 - ...

Page 24

Revision History Date Version - 16v8_10 August 2006 16v8_11 Specifications GAL16V8 Change Summary Previous Lattice release. Updated for lead-free package options. 24 ...

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