AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 110
AT83EC5123
Manufacturer Part Number
AT83EC5123
Description
(AT8xx512x) Smart Card Reader ICs
Manufacturer
ATMEL Corporation
Datasheet
1.AT83EC5123.pdf
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Mode 0 (13-bit Timer)
Figure 71. Timer/Counter x (x= 0 or 1) in Mode 0
Figure 72. Mode 0 Overflow Period Formula
Mode 1 (16-bit Timer)
110
INTx#
AT8xC5122/23
FCK_Tx
Tx
TMOD reg
GATEx
/6
TMOD reg
C/Tx#
For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer
operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets the TF0 flag and generates
an interrupt request.
It is important to stop the Timer/Counter before changing modes.
Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 reg-
ister) with a modulo-32 prescaler implemented with the lower five bits of the TL0 register
(see Figure 71). The upper three bits of the TL0 register are indeterminate and should
be ignored. Prescaler overflow increments the TH0 register.
Figure 72 gives the overflow period calculation formula.
Mode 1 configures Timer 0 as a 16-bit Timer with the TH0 and TL0 registers connected
in a cascade (see Figure 73). The selected input increments the TL0 register.
Figure 74 gives the overflow period calculation formula when in timer mode.
0
1
TCON reg
TRx
TFx
PER
=
6
(16384 – (THx, TLx))
F
CK_Tx
(8 bits)
THx
(5 bits)
TLx
Overflow
TCON reg
TFx
Timer x
Interrupt
Request
4202B–SCR–07/03
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