AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 123

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

INT1 Interrupt Vector
INT1/OE Input
RXD Input
CPRES Input
Registers
4202B–SCR–07/03
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority Low registers (Table 95 on page
127 and Table 97 on page 129) and in the Interrupt Priority High register (Table 96 on
page 128 and Table 99 on page 131) shows the bit values and priority levels associated
with each combination.
The INT1 interrupt is multiplexed with the following three inputs:
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•
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The setting configurations for each input is detailed below.
This interrupt input is active under the following conditions :
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The Bit IE1 (TCON Register) is set by hardware when external interrupt detected. It is
cleared when interrupt is processed.
A second vector interrupt input is the reception of a character. UART Rx input can gen-
erate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA
must also be set.
Then, the Bit RXIT (ISEL Register) is set by hardware when a low level is detected on
P3.0/RXD input.
The third input is the detection of a level change on CPRES input (P1.2). This input can
generate an interrupt if enabled with PRESEN (ISEL.1) , EX1 (IE0.2) and EA (IE0.7)
Bits.
This detection is done according to the level selected with Bit CPLEV (ISEL.7).
Then the Bit PRESIT (ISEL.5) is set by hardware when the triggering conditions are
met. This Bit must be cleared by software.
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced first. Thus within each priority level there is a second priority structure deter-
mined by the polling sequence.
INT1/OE: Standard 8051 interrupt input
RXD: Received data on UART
CPRES: Insertion or remove of the main card
It must be enabled by OEEN Bit (ISEL Register)
It can be active on a level or falling edge following IT1 Bit (TCON Register) status
If level triggering selection is set, the active level 0 or 1 can be selected with OELEV
Bit (ISEL Register)
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