AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 58

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

Description
Figure 30. USB Device Controller Block Diagram
Serial Interface Engine (SIE)
58
AT8xC5122/23
D+
D-
USB
D+/D-
Buffer
The only possible value for the wMaxPacketSize in the DFU configuration is 32 bytes,
which is the size of the FIFO implemented for endpoint 0.
The USB device controller provides the hardware that the AT8xC5122 and the
AT8xC5123 need to interface a USB link to a data flow stored in a double port memory
(DPRAM).
The USB controller requires a 48 MHz reference clock, which is the output of the
AT8xC5122/23 PLL (see Section "PLL", page 32) divided by a clock prescaler. This
clock is used to generate a 12 MHz full speed bit clock from the received USB differen-
tial data and to transmit data according to full speed USB device tolerance. Clock
recovery is done by a Digital Phase Locked Loop (DPLL) block, which is compliant with
the jitter specification of the USB bus.
The Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing,
CRC generation and checking, and the serial-parallel data conversion. The Universal
Function Interface (UFI) performs the interface between the data flow and the Dual Port
Ram
The SIE performs the following functions:
•
•
•
•
•
•
•
DPLL
SIE
NRZI data encoding and decoding.
Bit stuffing and unstuffing.
CRC generation and checking.
Handshakes.
TOKEN type identifying.
Address checking.
Clock generation (via DPLL).
48 MHz
12MHz
+/- 0.25%
UFI
C51
Microcontroller
Interface
Up to 48 MHz
UC_SYSCLK
4202B–SCR–07/03