AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 8

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

Table 1. Pinout Description (Continued)
8
PSEN
V
AVCC
XTAL
XTAL
Port
PLLF
P5.6
P5.7
RST
ALE
D+
EA
D-
REF
1
2
34
60
59
61
31
32
63
21
15
54
55
5
4
AT8xC5122/23
16
29
28
30
14
15
26
27
-
-
-
-
-
14
13
45
42
43
32
24
67
68
5
4
6
8
19
17
18
27
28
2
1
3
-
-
-
-
-
Internal
Supply
Power
DVCC
DVCC
AVCC
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
ESD
2KV
2KV
PWR
I/O
I/O
I/O
I/O
I/O
I/0
O
O
O
O
O
I
I
Reset
Level
1
1
Reset Input
Holding this pin low for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than V
This pin has an internal pull-up resistor which allows the device to be reset
by connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-Down mode returns
the chip to normal operation.
The output is active for at least 12 oscillator periods when an internal reset
occurs.
USB Positive Data Upstream Port
This pin requires an external 1.5 k
USB Negative Data Upstream Port
USB Voltage Reference: 3.0 <
V
controlled by software.
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, its output is connected to this pin.
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, leave XTAL2 unconnected.
External Access Enable
EA must be strapped to ground in order to enable the device to fetch code
from external memory locations 0000h to FFFFh.
If security level 1 is programmed, EA will be latched on reset.
Address Latch Enable/Program Pulse: Output pulse for latching the low
byte of the address during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
oscillator frequency, and can be used for external timing or clocking. Note
that one ALE pulse is skipped during each access to external data memory.
This pin is also the program pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this
bit set, ALE will be inactive during internal fetches
Program Strobe Enable: The read strobe to external program memory.
When executing code from the external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
PLL Low Pass Filter input
Receives the RC network of the PLL low pass filter.
Analog Supply Voltage
AVCC is used to supply the on-chip PLL and the USB drivers
REF
KB6
KB7
Alt
can be connected to D+ with a 1.5 k
Config
Reset
Port51
Port51
IL
is applied, whether or not the oscillator is running.
Push-pull
Push-pull
Conf 1
V
REF
pull-up to
< 3.6 V
Conf 2
Input
WPD
Input
WPD
resistor. The
V
REF
for full speed
Conf 3
WPU
WPU
Input
Input
V
4202B–SCR–07/03
REF
voltage is
Led