AT89C5131-PLTIL ATMEL Corporation, AT89C5131-PLTIL Datasheet - Page 22

• Manufacturer Part Number: AT89C5131-PLTIL
• Description: 8-bit Flash Microcontroller with Full Speed USB Device
• Manufacturer: ATMEL Corporation

Registers
22
AT89C5131
Table 28. CKCON0 (S:8Fh)
Clock Control Register 0
Reset Value = 0000 0000b
Bit Number
7
-
7
6
5
4
3
2
1
0
Mnemonic Description
PCAX2
WDX2
WDX2
T2X2
T1X2
T0X2
SIX2
Bit
X2
6
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Watchdog Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2)
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer2 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer0 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
System Clock Control bit
Clear to select 12 clock periods per machine cycle (STD mode, F
F
Set to select 6 clock periods per machine cycle (X2 mode, F
OSC
PCAX2
/
5
2).
SIX2
4
T2X2
3
T1X2
2
T0X2
CPU =
1
4136B–USB–09/03
CPU
F
PER =
= F
F
PER =
X2
OSC
0
).