HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 131

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

MOS pull-ups are automatically turned off.
In mode 3 (single-chip mode) with the dual-port RAM disabled (DPME = "0"), these pins can be
used for general-purpose input or output.
In slave mode (mode 3 with DPME = "1"), these pins are used for input of the CS and OE dual-port
RAM interface control signals. They are unaffected by the values in P9DDR and P9DR, except
that software can turn on their MOS pull-ups by clearing their data direction bits to "0" and setting
their data bits to "1."
Pin P9
or RDY dual-port RAM interface control signal. It is unaffected by the values in P9DDR and
P9DR, and its MOS pull-up is automatically turned off.
In mode 3 with the dual-port RAM disabled (DPME = "0"), this pin can be used for general-
purpose input or output.
Pin P9
automatically turned off.
In mode 3, this pin is used for general-purpose input if P9
output if P9
Pin P9
signal or WE dual-port RAM interface control signal. It is unaffected by the values in P9DDR and
P9DR, except that software can turn on its MOS pull-up by clearing its data direction bit to "0" and
setting its data bit to "1."
In mode 3 (single-chip mode) with the dual-port RAM disabled (DPME = "0"), this pin can be used
for general-purpose input or output.
Reset: In the single-chip mode (mode 3), a reset initializes all pins of port 9 to the general-purpose
input function with the MOS pull-ups off. In the expanded modes (modes 1 and 2), P9
initialized as input port pins, and P9
output functions.
Hardware Standby Mode: All pins are placed in the high-impedance state with their MOS pull-
ups off.
5
6
7
: In modes 1 and 2 and slave mode, this pin is used for output of the AS bus control signal
: In modes 1 and 2, this pin is used for system clock (Ø) output. Its MOS pull-up is
: In modes 1 and 2 and slave mode, this pin is used for input of the WAIT bus control
6
DDR is set to "1."
3
to P9
7
are initialized to their bus control and system clock
116
6
DDR is cleared to "0," or system clock
0
to P9
2
are