HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 142

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

6.2.2 Output Compare Registers A and B (OCRA and OCRB) – H’FF94
Bit
Initial 1
value
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output compare
flag (OCFA or OCFB) is set in the timer control/status register (TCSR).
In addition, if the output enable bit (OEA or OEB) in the timer output compare control register
(TOCR) is set to “1,” when the output compare register and FRC values match, the logic level
selected by the output level bit (OLVLA or OLVLB) in the TOCR is output at the output compare
pin (FTOA or FTOB).
OCRA and OCRB share the same address. They are differentiated by the OCRS bit in the TOCR.
A temporary register (TEMP) is used for write access, as explained in section 6.3, "CPU Interface."
OCRA and OCRB are initialized to H’FFFF at a reset and in the standby modes.
6.2.3 Input Capture Registers A to D (ICRA to ICRD) – H’FF98, H’FF9A, H’FF9C, H’FF9E
Bit
Initial 0
value
Read/ R
Write
Each input capture register is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected, the
current value of the FRC is copied to the corresponding input capture register (ICRA to ICRD). At
the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status
register (TCSR) is set to “1.” The input capture edge is selected by the input edge select bits
(IEDGA to IEDGD) in the timer interrupt enable register (TIER).
15
15
14
14
R
1
0
13
13
R
1
0
12
12
R
1
0
11
11
R
1
0
10
10
R
1
0
R
9
1
9
0
127
R
8
1
8
0
R
7
1
7
0
R
6
1
6
0
R
5
1
5
0
R
4
1
4
0
R
3
1
3
0
R
2
1
2
0
R
1
1
1
0
R
0
1
0
0