HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 144

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

The input capture registers are initialized to H’0000 at a reset and in the standby modes.
Note: When input capture is detected, the FRC value is transferred to the input capture register
even if the input capture flag is already set.
6.2.4 Timer Interrupt Enable Register (TIER) – H’FF90
Bit
Initial value
Read/Write
The TIER is an 8-bit readable/writable register that enables and disables interrupts.
The TIER is initialized to H’01 (all interrupts disabled) at a reset and in the standby modes.
Bit 7 – Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input
capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register
(TCSR) is set to “1.”
Bit 7
ICIAE
Bit 6 – Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input
capture interrupt B (ICIB) when input capture flag B (ICFB) in the timer status/control register
(TCSR) is set to “1.”
Bit 6
ICIBE
Bit 5 – Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input
capture interrupt C (ICIC) when input capture flag C (ICFC) in the timer status/control register
(TCSR) is set to “1.”
0
1
0
1
Description
Input capture interrupt request A (ICIA) is disabled.
Input capture interrupt request A (ICIA) is enabled.
Description
Input capture interrupt request B (ICIB) is disabled.
Input capture interrupt request B (ICIB) is enabled.
ICIAE
R/W
7
0
ICIBE
R/W
6
0
ICICE
R/W
5
0
ICIDE
129
R/W
4
0
OCIAE OCIBE
R/W
3
0
R/W
2
0
OVIE
R/W
1
0
(Initial value)
(Initial value)
—
—
0
1