HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 156

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

6.4.2 Output Compare Timing
(1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags
are set to “1” by an internal compare-match signal generated when the FRC value matches the
OCRA or OCRB value. This compare-match signal is generated at the last state in which the two
values match, just before the FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 6-8 shows the timing of the setting of the output
compare flags.
(2) Timing of Output Compare Flag (OCFA or OCFB) Clearing: The output compare flag
OCFA or OCFB is cleared when the CPU writes a “0” in this bit.
OCRA or OCRB
FRC
OCR
Internal compare-
match signal
Ø
OCFA or OCFB
Ø
OCFA or OCFB
Figure 6-9. Clearing of Output Compare Flag
Figure 6-8. Setting of Output Compare Flags
Write cycle: CPU writes "0" in OCFA or OCFB
N
N
T
1
141
T
2
T
3
N + 1