HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 170

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

7.2.2 Time Constant Registers A and B (TCORA and TCORB) – H’FFCA and H’FFCB
Bit
Initial value
Read/Write
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
compared with the constants written in these registers. When a match is detected, the
corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register
(TCSR).
The timer output signal (TMO0 or TMO1) is controlled by these compare-match signals as
specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).
TCORA and TCORB are initialized to H’FF at a reset and in the standby modes.
Compare-match is not detected during the T3 state of a write cycle to TCORA or TCORB. See
item (3) in section 7.6, "Application Notes."
7.2.3 Timer Control Register (TCR) – H’FFC8 (TMR0), H’FFD0 (TMR1)
Bit
Initial value
Read/Write
Each TCR is an 8-bit readable/writable register that selects the clock source and the time at which
the timer counter is cleared, and enables interrupts.
The TCRs are initialized to H’00 at a reset and in the standby modes.
Bit 7 – Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
control/status register (TCSR) is set to “1.”
(TMR0), H’FFD2 and H’FFD3 (TMR1)
CMIEB CMIEA
R/W
R/W
7
1
7
0
R/W
R/W
6
1
6
0
OVIE
R/W
R/W
5
5
1
0
CCLR1 CCLR0
156
R/W
R/W
4
1
4
0
R/W
R/W
3
1
3
0
CKS2
R/W
R/W
2
1
2
0
CKS1
R/W
R/W
1
1
1
0
CKS0
R/W
R/W
0
1
0
0