HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 172

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

Bit 2
CKS2
0
0
0
0
1
1
1
1
7.2.4 Timer Control/Status Register (TCSR) – H’FFC9 (TMR0), H’FFD1 (TMR1)
Bit
Initial value
Read/Write
* Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
The TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
The TCSR is initialized to H’10 at a reset and in the standby modes.
Bit 7 – Compare-Match Flag B (CMFB): This status flag is set to “1” when the timer count
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 7
CMFB
Bit 6 – Compare-Match Flag A (CMFA): This status flag is set to “1” when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
0
1
Bit 1
CKS1
0
0
1
1
0
0
1
1
Description
To clear CMFB, the CPU must read CMFB after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when TCNT = TCORB.
R/(W)* R/(W)* R/(W)*
CMFB
7
0
Bit 0
CKS0
0
1
0
1
0
1
0
1
CMFA
6
0
Description
No clock source (timer stopped)
Ø/8 Internal clock source, counted on the falling edge
Ø/64 Internal clock source, counted on the falling edge
Ø/1024 Internal clock source, counted on the falling edge
No clock source (timer stopped)
External clock source, counted on the rising edge
External clock source, counted on the falling edge
External clock source, counted on both the rising
and falling edges
OVF
5
0
158
—
—
4
1
R/W
OS3
3
0
R/W
OS2
2
0
R/W
OS1
1
0
(Initial value)
(Initial value)
R/W
OS0
0
0