HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 179

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HD6413308

Manufacturer Part Number
HD6413308
Description
Hitachi Single-Chip MicroComputer
Manufacturer
Hitachi Semiconductor
Datasheet

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7.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding
enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller
for each interrupt. Table 7-3 lists information about these interrupts.
Table 7-3. 8-Bit Timer Interrupts
Interrupt
CMIA
CMIB
OVI
7.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor.
The control bits are set as follows:
(1) In the TCR, CCLR1 is cleared to “0” and CCLR0 is set to “1” so that the timer counter is
(2) In the TCSR, bits OS3 to OS0 are set to “0110,” causing the output to change to “1” on
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a
pulse width determined by TCORB. No software intervention is required.
cleared when its value matches the constant in TCORA.
compare-match A and to “0” on compare-match B.
OVF
Ø
Description
Requested when CMFA and CMIEA are set
Requested when CMFB and CMIEB are set
Requested when OVF and OVIE are set
Figure 7-11. Clearing of Overflow Flag
When cycle: CPU writes "0" in OVF
T
1
T
165
2
T
3
Priority
High
Low

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