HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 201

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

Bit 5 – Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5
ORER
Bit 4 – Framing Error (FER): This bit indicates a framing error during data reception in the
asynchronous mode. It has no meaning in the synchronous mode.
Bit 4
FER
Bit 3 – Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without parity
bits is used.
Bit 3
PER
Bits 2 to 0 – Reserved: These bits cannot be modified and are always read as “1.”
0
1
0
1
0
1
Description
To clear ORER, the CPU must read ORER after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 if reception of the next character ends while
the receive data register is still full (RDRF = “1”).
Description
To clear FER, the CPU must read FER after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 if a framing error occurs (stop bit = “0”).
Description
To clear PER, the CPU must read PER after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when a parity error occurs (the parity of the
received data does not match the parity selected by the O/E bit
in the SMR).
188
(Initial value)
(Initial value)
(Initial value)