HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 216

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

Table 9-9. SCI Interrupts
Interrupt
ERI
RxI
TxI
Figure 9-5 shows the timing of the RxI interrupt signal. The timing of TxI and ERI is similar.
9.5 Application Notes
Application programmers should note the following features of the SCI.
(1) TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents
have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE
value. If a new byte is written in the TDR while the TDRE bit is “0,” before the old TDR contents
have been moved into the TSR, the old byte will be lost. Normally, software should check that the
TDRE bit is set to “1” before writing to the TDR.
(2) Multiple Receive Errors: Table 9-10 lists the values of flag bits in the SSR when multiple
receive errors occur, and indicates whether the RSR contents are transferred to the RDR.
Ø
Internal
Receive-
End
signal
RDRF
RxI
Description
Receive-error interrupt, requested when ORER, FER, or PER
is set. RIE must also be set.
Receive-end interrupt, requested when RDRF and RIE are set.
Transmit-end interrupt, requested when TDRE and TIE are set.
Figure 9-5. Timing of Interrupt Signal
203
Figure 9-5
Priority
High
Low