HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 238

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HD6413308

Manufacturer Part Number
HD6413308
Description
Hitachi Single-Chip MicroComputer
Manufacturer
Hitachi Semiconductor
Datasheet

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11.1.3 Input and Output Pins
Table 11-1 lists the input and output pins of the dual-port RAM.
Table 11-1. Dual-Port RAM Input and Output Pins
Name
DPRAM data bus
Chip select
Register select
Output enable
Write enable
Ready
* NMOS open drain output.
11.1.4 Register Configuration
Table 11-2 lists the registers of the dual-port RAM.
Table 11-2. Dual-Port RAM Register Configuration
Name
Parallel communication PCCSR R/(W)* R/(W)* H’00
control/status register
Parallel communication PCDR0A R
data register 0
Parallel communication PCDR1 R/W
data register 1
Parallel communication PCDR2 R/W
data register 2
Parallel communication PCDR3 R/W
data register 3
Abbreviation
DDB
CS
RS
OE
WE
RDY
Abbr.
PCDR0B W
3
to RS
7
to DDB
0
H8/300 Master Initial
CPU
Read/write
0
Input/output An 8-bit parallel data bus by which the
Input
Output *
I/O
Input
Input
Input
CPU
W
R
R/W
R/W
R/W
227
value
Undeter- H’FFF1
mined
Undeter- H’FFF2
mined
Undeter- H’FFF3
mined
Undeter- H’FFF4
mined
Function
master CPU can access the dual-port
RAM.
Chip select input pin for selecting the
dual-port RAM.
Dual-port RAM address input.
Enables output on the DPRAM data bus.
Enables data to be written in the dual-port
RAM via the DPRAM data bus.
Indicates that the dual-port RAM is ready
to be written or read by the master CPU.
(NMOS open-drain output)
On-chip
address RS
H’FFF0 0
H’FFF1
0
0
0
0
0
External address
3
RS
0
0
0
0
0
1
2
RS
0
0
0
1
1
0
1
RS
0
1
1
0
1
0
0

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