HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 59

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

Before Execution of BCLR Instruction
Input/output
Pin state
DDR
DR
Pull-up Mos
Execution of BCLR Instruction
BCLR.B
After Execution of BCLR Instruction
Input/output
Pin state
DDR
DR
Pull-up Mos
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P4
are set to "1," making P4
Example 2: BSET is executed to set bit 0 in the port 4 data register (P4DR) under the following
conditions.
P4
P4
P4
The intended purpose of this BSET instruction is to switch the output level at P4
High.
7
6
5
:
:
– P4
0
:
#0, @P4DDR
0
Input pin, Low, MOS pull-up transistor on
Input pin, High, MOS pull-up transistor off
Output pins, Low
DDR is cleared to "0," making P4
P4
Input
Low
0
1
On
P4
Output Output Output Output Output Output Output Input
Low
1
1
Off
7
7
7
and P4
P4
Input
High
0
0
Off
P4
High
1
0
Off
6
6
;clear bit 0 in data direction register
6
output pins.
P4
Output Output Output Output Output Output
Low
1
0
Off
P4
Low
1
0
Off
5
5
P4
Low
1
0
Off
P4
Low
1
0
Off
4
4
43
0
an input pin. In addition, P4
P4
Low
1
0
Off
P4
Low
1
0
Off
3
3
P4
Low
1
0
Off
P4
Low
1
0
Off
2
2
P4
Low
1
0
Off
P4
Low
1
0
Off
1
1
7
P4
1
0
Off
P4
0
0
Off
Low
High
DDR and P4
0
from Low to
0
0
6
DDR