HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 86

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

accepted the interrupt mask (I bit) is set, so the NMI handling routine cannot be interrupted except
by another NMI.
The NMI vector number is 3. Its entry is located at address H’0006 in the vector table.
(2) IRQ
to IRQ
: These interrupt signals are level-sensed or sensed on the falling edge of the
0
7
input, as selected by the bits in the ISCR. These interrupts can be masked collectively by the I bit
in the CCR, and can be enabled and disabled individually by setting and clearing the bits in the
IER. When one of these interrupts is accepted, the I bit is set to "1" to mask further interrupts
(except NMI).
The interrupt controller reads level-sensed signals directly from the input pin, so the signal must be
held Low until the interrupt is accepted.
Edge-sensed signals are latched in a flip-flop in the interrupt controller. The signal is latched only
if the interrupt is enabled in the IRQ enable register. However, the signal is latched even if the
interrupt is masked (I bit set to “1” in the CCR).
These interrupts are second in priority to NMI. Among them, IRQ
has the highest priority and
0
IRQ
the lowest priority.
7
Interrupts IRQ
to IRQ
occur regardless of whether the IRQ
to IRQ
lines are used for input or
0
7
0
7
output. When IRQ
to IRQ
are requested by external signals, clear the corresponding bits in the
0
7
port data direction register (DDR) to 0, and do not use the same pins for timer or serial
communication interface input or output.
4.2.3 Internal Interrupts
Nineteen internal interrupts can be requested by the on-chip supporting modules. All of them are
masked when the I bit in the CCR is set. In addition, they can all be enabled or disabled by bits in
the control registers of the on-chip supporting modules. When one of these interrupts is accepted,
the I bit is set to "1" to mask further interrupts (except NMI).
Power can be conserved by waiting for an internal interrupt in the sleep mode, in which the CPU
halts but the on-chip supporting modules continue to run. When the interrupt arrives, the CPU
returns to the program-execution state, services the interrupt, then resumes execution of the main
program. See section 14, “Power-Down State” for further information on the sleep mode.
The internal interrupt signals received by the interrupt controller are generated from flag bits in the
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