HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 188

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

9.1.4
Table 9.2 summarizes the DMAC registers. DMAC has a total of 17 registers. Each channel has
four control registers. One other control register is shared by all channels
Table 9.2
Chan-
nel
0
1
2
3
Shared DMA operation register
Notes: 1. Write 0 alone in bit 1 of CHCR0–CHCR3 to clear flags.
2. Write 0 alone in bits 1 and 2 of the DMAOR to clear flags.
3. Access SAR0–SAR3, DAR0–DAR3, and TCR0–TCR3 by long word or word. If byte
Name
DMA source address register 0
DMA destination address
register 0
DMA transfer count register 0
DMA channel control register 0
DMA source address register 1
DMA destination address
register 1
DMA transfer count register 1
DMA channel control register 1
DMA source address register 2
DMA destination address
register 2
DMA transfer count register 2
DMA channel control register 2
DMA source address register 3
DMA destination address
register 3
DMA transfer count register 3
DMA channel control register 3
Register Configuration
access is used when writing, the value of the register contents becomes undefined; if
used when reading, the value read is undefined.
DMAC Registers
Abbre-
viation
SAR0*
DAR0*
TCR0*
CHCR0
SAR1*
DAR1*
TCR1*
CHCR1
SAR2*
DAR2*
TCR2*
CHCR2
SAR3*
DAR3*
TCR3*
CHCR3
DMAOR R/(W)*
3
3
3
3
3
3
3
3
3
3
3
3
R/W
R/W
R/W
R/W
R/(W)*
R/W
R/W
R/W
R/(W)*
R/W
R/W
R/W
R/(W)*
R/W
R/W
R/W
R/(W)*
1
1
1
1
2
Initial
Value
Undefined H'5FFFF40
Undefined H'5FFFF44
Undefined H'5FFFF4A 16, 32
H'0000
Undefined H'5FFFF50
Undefined H'5FFFF54
Undefined H'5FFFF5A 16, 32
H'0000
Undefined H'5FFFF60
Undefined H'5FFFF64
Undefined H'5FFFF6A 16, 32
H'0000
Undefined H'5FFFF70
Undefined H'5FFFF74
Undefined H'5FFFF7A 16, 32
H'0000
H'0000
Address
H'5FFFF4E 8, 16, 32
H'5FFFF5E 8, 16, 32
H'5FFFF6E 8, 16, 32
H'5FFFF7E 8, 16, 32
H'5FFFF48
HITACHI 173
Access
Size
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
8, 16, 32