HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 208
HD6417021
Manufacturer Part Number
HD6417021
Description
SuperH RISC engine
Manufacturer
Hitachi Semiconductor
Datasheet
1.HD6417021.pdf
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D15–D0
The DACK output when a transfer occurs from an external device with DACK to a memory-
mapped external device is the write waveform. The DACK output when a transfer occurs from
a memory-mapped external device to an external device with DACK is the read waveform.
The setting of the acknowledge mode (AM) bits in the channel control registers (CHCR0,
CHCR1) have no effect.
A21–A0
DACK
D15–D0
A21–A0
CSn
DACK
RD
WRH
CK
WRL
CSn
Figure 9.7 Example of DMA Transfer Timing in the Single Address Mode
CK
(b) External memory space to external device with DACK
(a) External device with DACK to external memory space
Address output to external memory space
Data that is output from external memory space
RD signal to external memory space
DACK signal to external device with DACK
(active low)
Address output to external memory space
Data that is output from the external
device with DACK
DACK signal to external devices with
DACK (active low)
WR signal to external memory space
HITACHI 193
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