HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 217
HD6417021
Manufacturer Part Number
HD6417021
Description
SuperH RISC engine
Manufacturer
Hitachi Semiconductor
Datasheet
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202 HITACHI
detection and DACK active low) (Single address mode, bus cycle = DRAM bus cycle (long
detection and DACK active low) (Dual address mode, bus cycle = DRAM bus cycle (long
Note:
Note:
Figure 9.19 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
Figure 9.20 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
Bus cycle
Bus cycle
DREQ
DREQ
DACK
DACK
When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer
will be executed because the sampling is done at the second state of the DMAC cycle.
When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer
will be executed because the sampling is done at the second state of the DMAC cycle.
CK
CK
CPU
CPU
CPU
CPU
CPU
CPU
pitch normal mode))
pitch normal mode))
Tp
DMAC(R)
Tr
Tp
Tc
DMAC
Tr
Tc
Tc
DMAC
(W)
Tc
CPU
CPU
DMAC (W): DMAC write cycle
DMAC (R): DMAC read cycle
Tp
DMAC (R)
Tp
Tr
Tc
DMAC
Tr
Tc
Tc
DMAC
Tc
(W)
CPU
CPU
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